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m
Added the rest of the pretty much known stuff. Timers still :/
Line 50:
Line 50:
{{regdesc
{{regdesc
|ChX|00: Access Denied, 01: Read Only, 10: Write Only, 11: Read/Write
|ChX|00: Access Denied, 01: Read Only, 10: Write Only, 11: Read/Write
+}}
+
+{{reg16 | MI_INTMASK | addr = 0x0C00401C | fields = 6 |
+|11 |1 |1 |1 |1 |1 |
+|U |?/W |?/W |?/W |?/W |?/W |
+| |ChAll |Ch3 |Ch2 |Ch1 |Ch0 |
+|}}
+{{regdesc
+|ChX|When set, interrupt from that channel is enabled.
+|ChAll|When set, all MI interrupts are enabled.
+}}
+{{reg16 | MI_INTFLAG | addr = 0x0C00401E | fields = 6 |
+|11 |1 |1 |1 |1 |1 |
+|U |R/W |R/W |R/W |R/W |R/W |
+| |ChAll |Ch3 |Ch2 |Ch1 |Ch0 |
+|}}
+{{regdesc
+|ChX|When set, IRQ has been requested. Writing 1 clears it.
+|ChAll|All MI interrupts. (?)
+}}
+{{reg16 | MI_UNKNOWN1 | addr = 0x0C004020 | fields = 3 |
+|14 |1 |1 |
+|U |? |U |
+| |Unk | |
+|}}
+{{regdesc
+|Unk|? Set when MI interrupt has been asserted ? Should be cleared by interrupt handler
+}}
+
+{{reg16 | MI_PROT_ADDRLO | addr = 0x0C004022 | fields = 2 |
+|11 |5 |
+|R/? |U |
+|Low | |
+|}}
+{{reg16 | MI_PROT_ADDRHI | addr = 0x0C004024 | fields = 2 |
+|2 |14 |
+|U |R/? |
+| |High |
+|}}
+{{regdesc
+|High|Bits 29->16 of the address that the protection exception occurred on.
+|Low|Bits 15->5 of the address that the protection exception occurred on.
}}
}}