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Line 7:
}}
}}
{{hwstub}}
{{hwstub}}
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{{yagcd}}
Protected memory is always 1 page long (page size is 1024 bytes), and you can specify only 4 protected regions. If the CPU tries to access the protected region in a way that is not allowed, an external interrupt will be raised. Because there are only 4 protected regions, there are a total of 4 possible interrupts which are called MEM_0, MEM_1, MEM_2 and MEM_3.
Protected memory is always 1 page long (page size is 1024 bytes), and you can specify only 4 protected regions. If the CPU tries to access the protected region in a way that is not allowed, an external interrupt will be raised. Because there are only 4 protected regions, there are a total of 4 possible interrupts which are called MEM_0, MEM_1, MEM_2 and MEM_3.
== Registers ==
== Registers ==
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|High|Bits 29->16 of the address that the protection exception occurred on.
|High|Bits 29->16 of the address that the protection exception occurred on.
|Low|Bits 15->5 of the address that the protection exception occurred on.
|Low|Bits 15->5 of the address that the protection exception occurred on.
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}}
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{{regsimple | MI_TIMER0 | addr = 0x0C004032 | bits = 32 | access = R/?}}
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{{regsimple | MI_TIMER1 | addr = 0x0C004036 | bits = 32 | access = R/?}}
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{{regsimple | MI_TIMER2 | addr = 0x0C00403A | bits = 32 | access = R/?}}
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{{regsimple | MI_TIMER3 | addr = 0x0C00403E | bits = 32 | access = R/?}}
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{{regsimple | MI_TIMER4 | addr = 0x0C004042 | bits = 32 | access = R/?}}
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{{regsimple | MI_TIMER5 | addr = 0x0C004046 | bits = 32 | access = R/?}}
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{{regsimple | MI_TIMER6 | addr = 0x0C00404A | bits = 32 | access = R/?}}
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{{regsimple | MI_TIMER7 | addr = 0x0C00404E | bits = 32 | access = R/?}}
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{{regsimple | MI_TIMER8 | addr = 0x0C004052 | bits = 32 | access = R/?}}
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{{regsimple | MI_TIMER9 | addr = 0x0C004056 | bits = 32 | access = R/?}}
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{{regdesc
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|Timer|Writing anything to a timer resets it to 0.
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}}
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{{reg16 | MI_UNKNOWN2 | addr = 0x0C00405A | fields = 2 |
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|5 |5 |
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|U |R/? |
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|? |Unk |
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|}}
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{{regdesc
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|Unk|Possibly something timer related?
}}
}}