Line 27:
Line 27:
This register controls the state of the NAND interface.
This register controls the state of the NAND interface.
{{regdesc
{{regdesc
−
|EXEC|Write 1: initiate NAND command<br/>Read: NAND interface busy
+
|EXEC|Write 1: initiate NAND command<br/>Write 0: reset NAND interface<br/>Read: NAND interface busy
|IRQ|Set to enable IRQ generation when command is complete
|IRQ|Set to enable IRQ generation when command is complete
|ERR|If set, NAND error occured (?){{check}}
|ERR|If set, NAND error occured (?){{check}}