892
edits
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Line 23:
Line 23:
|1|1|1|1|12|
|1|1|1|1|12|
|R/W|R/W|R/W|R/W|W|
|R/W|R/W|R/W|R/W|W|
−|WAIT|WR|RD|ECC|DMALEN|
+|WAIT|WR|RD|ECC|DATALEN|
}}
}}
This register controls the state of the NAND interface.
This register controls the state of the NAND interface.
Line 40:
Line 40:
|RD|Transfer data from the NAND chip
|RD|Transfer data from the NAND chip
|ECC|Calculate ECC or ?? {{check}}
|ECC|Calculate ECC or ?? {{check}}
−|DMALEN|Number of bytes to transfer
+|DATALEN|Number of bytes to transfer during the data phase
}}
}}
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