Changes

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{{regsimple | NAND_DATABUF | addr = 0x0d010010 | bits = 32 | access = R/W }}

{{regsimple2 | NAND_DATABUF | addr = 0x0d010010 | bits = 32 | split=4 | access = U | accesshi = R/W }}

This register contains the DMA address of the page data buffer (0x800 bytes).

This register contains the DMA address of the page data buffer (0x800 bytes). The address must be 16-byte aligned.

If the spare data is being written alone (such as using a RANDOM DATA IN command with DMALEN=0x40), this points to it instead. Generally speaking, the first 0x800 bytes of data go here, whatever they may be.

If the spare data is being written alone (such as using a RANDOM DATA IN command with DMALEN=0x40), this points to it instead. Generally speaking, the first 0x800 bytes of data go here, whatever they may be.

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{{regsimple | NAND_ECCBUF | addr = 0x0d010014 | bits = 32 | access = R/W }}

{{regsimple2 | NAND_ECCBUF | addr = 0x0d010014 | bits = 32 | split=4 | access = U | accesshi = R/W }}

This register contains the DMA address of the spare and ECC data buffer (0x40 spare bytes + 0x10 bytes of hardware-calculated ECC syndrome).

This register contains the DMA address of the spare and ECC data buffer (0x40 spare bytes + 0x10 bytes of hardware-calculated ECC syndrome). The address must be 16-byte aligned.

The hardware-calculated ECC is written to the address in this register XOR 0x40.

The hardware-calculated ECC is written to the address in this register XOR 0x40.

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{{regsimple | NAND_UNK | addr = 0x0d010018 | bits = 32 | access = R/W }}

{{regsimple | NAND_UNK | addr = 0x0d010018 | bits = 32 | access = R/W }}

This register has an unknown function; boot2 writes 1 to it when reloading to a new IOS.

This register has an unknown function; boot2 writes 1 to it when reloading to a new IOS.