834
edits
Changes
add 0x0d010018
Line 2:
Line 2:
| arm = Full
| arm = Full
| base = 0x0d010000
| base = 0x0d010000
−| len = 0x20
+| len = 0x1C
| bits = 32
| bits = 32
| armirq = 1
| armirq = 1
Line 14:
Line 14:
{{rla|0x0d010010|32|NAND_DATABUF|Memory address of the Data buffer}}
{{rla|0x0d010010|32|NAND_DATABUF|Memory address of the Data buffer}}
{{rla|0x0d010014|32|NAND_ECCBUF|Memory address of the Spare buffer}}
{{rla|0x0d010014|32|NAND_ECCBUF|Memory address of the Spare buffer}}
+{{rla|0x0d010018|32|NAND_UNK|Unknown}}
|}
|}
== Register Details ==
== Register Details ==
Line 85:
Line 86:
{{regsimple | NAND_ECCBUF | addr = 0x0d010014 | bits = 32 | access = R/W }}
{{regsimple | NAND_ECCBUF | addr = 0x0d010014 | bits = 32 | access = R/W }}
This register contains the DMA address of the spare and ECC data buffer (0x40 spare bytes + 0x10 bytes of hardware-calculated ECC syndrome).
This register contains the DMA address of the spare and ECC data buffer (0x40 spare bytes + 0x10 bytes of hardware-calculated ECC syndrome).
+----
+{{regsimple | NAND_UNK | addr = 0x0d010018 | bits = 32 | access = R/W }}
+This register has an unknown function; boot2 writes 1 to it when reloading to a new IOS.