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Hardware/NAND Interface (view source)
Revision as of 22:03, 27 February 2009
, 22:03, 27 February 2009no edit summary
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== Register Details ==
== Register Details ==
−{{reg32 | NAND_CTRL | addr = 0x0d010000 | hifields = 9 | lofields = 2 |
+{{reg32 | NAND_CTRL | addr = 0x0d010000 | hifields = 9 | lofields = 5 |
|1|1|1|1|1|1|1|1|8|
|1|1|1|1|1|1|1|1|8|
|R/W|W|U|W|W|W|W|W|W|
|R/W|W|U|W|W|W|W|W|W|
|EXEC|IRQ||A5|A4|A3|A2|A1|COMMAND||
|EXEC|IRQ||A5|A4|A3|A2|A1|COMMAND||
−|4|12|
+|1|1|1|1|12|
−|W|W|
+|W|W|W|W|W|
−|FLAGS|DMALEN|
+|WAIT|WR|RD|ECC|DMALEN|
}}
}}
This register controls the state of the NAND interface.
This register controls the state of the NAND interface.
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|A1|Send first address byte (typ. column address low)
|A1|Send first address byte (typ. column address low)
|COMMAND|8-bit NAND command
|COMMAND|8-bit NAND command
−|FLAGS|TBD
+|WAIT|Wait for R/B to go high between address and data phases (wait for read/write/erase){{check}}
−|DMALEN|Number of bytes to copy
+|WR|Transfer data to the NAND chip{{check}}
+|RD|Transfer data from the NAND chip{{check}}
+|ECC|Calculate ECC or transfer ECC data or ?? {{check}}
+|DMALEN|Number of bytes to transfer
}}
}}
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