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Hardware/NAND Interface (view source)
Revision as of 18:20, 27 February 2009
, 18:20, 27 February 2009nand stuff
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+ + +! base !! function !! offset !! description !! contents/example+|-+|| || || || || 8030B840 (CMD 30: data (starts DMA 0x840 bytes))+|-+|-+|-+|-+|-+|-+|| || || 0018 W || unknown ||+|}+
| armirq = 1
| armirq = 1
}}
}}
−== Register List ==
{{reglist|NAND Interface}}
{{reglist|NAND Interface}}
{{rla|0x0d010000|32|NAND_CTRL|NAND Control and Status}}
{{rla|0x0d010000|32|NAND_CTRL|NAND Control and Status}}
−{{rld|0x0d010004|32|NAND_CONFIG|??}}
+{{rla|0x0d010004|32|NAND_CONFIG|??}}
−{{rld|0x0d010008|32|NAND_ADDR1|High address bytes}}
+{{rla|0x0d010008|32|NAND_ADDR1|Address bytes 1-2 (column)}}
−{{rld|0x0d01000C|32|NAND_ADDR2|Low address bytes}}
+{{rla|0x0d01000c|32|NAND_ADDR2|Address bytes 3-5 (row)}}
−{{rld|0x0d010010|32|NAND_DATABUF|Address of the Data buffer}}
+{{rla|0x0d010010|32|NAND_DATABUF|Memory address of the Data buffer}}
−{{rld|0x0d010014|32|NAND_ECCBUF|Address of the Spare buffer}}
+{{rla|0x0d010014|32|NAND_ECCBUF|Memory address of the Spare buffer}}
|}
|}
−== Register Details ==
−{{reg32 | NAND_CTRL | addr = 0x0d010000 | hifields = 5 | lofields = 2 |
+{{reg32 | NAND_CTRL | addr = 0x0d010000 | hifields = 9 | lofields = 2 |
−|1|1|1|5|8|
+|1|1|1|1|1|1|1|1|8|
−|R/W|W|U|W|W|
+|R/W|W|U|W|W|W|W|W|W|
−|EXEC|IRQ||ADDR_MASK|COMMAND||
+|EXEC|IRQ||A5|A4|A3|A2|A1|COMMAND||
|4|12|
|4|12|
|W|W|
|W|W|
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{{regdesc
{{regdesc
|EXEC|Write 1: initiate NAND command<br/>Read: NAND interface busy
|EXEC|Write 1: initiate NAND command<br/>Read: NAND interface busy
−|IRQ|Set to enable IRQ generation
+|IRQ|Set to enable IRQ generation when command is complete
−|ADDR_MASK|Mask of the address bytes to send (10 {{=}} AA, 08 {{=}} BB, ..., 01 {{=}} FF)
+|A5|Send fifth address byte (typ. row address high)
+|A4|Send fourth address byte (typ. row address mid)
+|A3|Send third address byte (typ. row address low)
+|A2|Send second address byte (typ. column address high)
+|A1|Send first address byte (typ. column address low)
|COMMAND|8-bit NAND command
|COMMAND|8-bit NAND command
|FLAGS|TBD
|FLAGS|TBD
|DMALEN|Number of bytes to copy
|DMALEN|Number of bytes to copy
}}
}}
−----
−{| border="1"
+{{reg32 | NAND_CONF | addr = 0x0d010004 | hifields = 1 | lofields = 1 |
−|16|
−|-
+|?|
−|0x0D010000||NAND ||
+|Unknown||
−|-
+|16|
−| || || 0000 W || command || 9F000000 (CMD 00: start read sector)
+|?|
−|Unknown|
−}}
−This register probably configures certain aspects of the NAND interface (timings?){{check}}. The bit definitions are unknown. This register is written with the values 0x08000000 and 0x4b3e0e7f during initialization.
−|| || || || || 80FF8000 (CMD FF: reset)
+----
−|-
+{{reg32 | NAND_ADDR1 | addr = 0x0d010008 | hifields = 1 | lofields = 2 |
−|| || || || || 00008000 means: wait for R/#B to go down
+|16|
−|-
+|U|
−|| || || || || 1F000000 is the mask of the address bytes to send. (10 = AA, 08 = BB, .., 01 = FF in 08,0c)
+|||
−|8|8|
−|| || || 0000 R || status || MSB means busy
+|R/W|R/W|
−|-
+|ADDR2|ADDR1|
−|| || || 0004 W || config ||
+}}
−|-
+This register contains the first two address bytes that can be sent to the NAND chip. Normally it contains the column address (offset within a page).
−|| || || 0008 W || address #0 || 0000AABB
+{{regdesc
−|ADDR2|Second address byte
−|| || || 000C W || address #1 || CCDDEEFF, NAND sector, multiply with 0x800 or 0x840 to get offset, 0x40 for ecc
+|ADDR1|First address byte
−}}
−|| || || 0010 W || data addr || target address for DMA (0x800 main bytes)
+----
−{{reg32 | NAND_ADDR2 | addr = 0x0d01000c | hifields = 2 | lofields = 2 |
−|| || || 0014 W || ecc addr || target address for DMA (0x40 spare bytes + 0x10 byte HW-calculated ECC syndrome)
+|8|8|
−|U|R/W|
−||ADDR5||
−|8|8|
+|R/W|R/W|
+|ADDR4|ADDR3|
+}}
+This register contains the last three address bytes that can be sent to the NAND chip. Normally it contains the row address (page number).
+{{regdesc
+|ADDR5|Fifth address byte
+|ADDR4|Fourth address byte
+|ADDR3|Third address byte
+}}
+----
+{{regsimple | NAND_DATABUF | addr = 0x0d010010 | bits = 32 | access = R/W }}
+This register contains the DMA address of the page data buffer (0x800 bytes)
+----
+{{regsimple | NAND_ECCBUF | addr = 0x0d010014 | bits = 32 | access = R/W }}
+This register contains the DMA address of the spare and ECC data buffer (0x40 spare bytes + 0x10 bytes of hardware-calculated ECC syndrome).