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Hardware/NAND Interface (view source)
Revision as of 03:51, 27 February 2009
, 03:51, 27 February 2009no edit summary
Line 8:
Line 8:
{{reglist|NAND Interface}}
{{reglist|NAND Interface}}
−{{rla|0x0d010000|32|NAND_CTRL}}
+{{rla|0x0d010000|32|NAND_CTRL|NAND Control and Status}}
−{{rld|0x0d010004|32|NAND_CONFIG}}
+{{rld|0x0d010004|32|NAND_CONFIG|??}}
−{{rld|0x0d010008|32|NAND_ADDR1}}
+{{rld|0x0d010008|32|NAND_ADDR1|High address bytes}}
−{{rld|0x0d01000C|32|NAND_ADDR2}}
+{{rld|0x0d01000C|32|NAND_ADDR2|Low address bytes}}
−{{rld|0x0d010010|32|NAND_DATABUF}}
+{{rld|0x0d010010|32|NAND_DATABUF|Address of the Data buffer}}
−{{rld|0x0d010014|32|NAND_ECCBUF}}
+{{rld|0x0d010014|32|NAND_ECCBUF|Address of the Spare buffer}}
|}
|}