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Line 8:
Line 8: − + − {{rld|0x80000000|1|NAND_COMMAND_ENABLE|this bit must be set for the command to be considered valid}} − {{rld|0x1F000000|5|NAND_ADDR_MASK|these bits tell the NAND interface which of the address bytes from NAND_ADDR1/2 should be sent with this command}} − {{rld|0x00FF0000|8|NAND_COMMAND|this is the actual 8-bit NAND command}} − {{rld|0x0000F000|4|NAND_COMMAND_FLAGS|tbd}} − {{rld|0x00000FFF|12|NAND_COMMAND_DMALEN|this tells the DMA engine how many bytes to copy}} − {{rld|0x0d010000 (R)|32|NAND_STATUS}} Line 21:
Line 15: + + + + + + + + + + + + + + + + + +
Hardware/NAND Interface (view source)
Revision as of 03:49, 27 February 2009
, 03:49, 27 February 2009no edit summary
{{reglist|NAND Interface}}
{{reglist|NAND Interface}}
{{rld|0x0d010000 (W)|32|NAND_COMMAND_BITMASK|a bitfield}}
{{rla|0x0d010000|32|NAND_CTRL}}
{{rld|0x0d010004|32|NAND_CONFIG}}
{{rld|0x0d010004|32|NAND_CONFIG}}
{{rld|0x0d010008|32|NAND_ADDR1}}
{{rld|0x0d010008|32|NAND_ADDR1}}
{{rld|0x0d010014|32|NAND_ECCBUF}}
{{rld|0x0d010014|32|NAND_ECCBUF}}
|}
|}
{{reg32 | NAND_CTRL | addr = 0x0d010000 | hifields = 5 | lofields = 2 |
|1|1|1|5|8|
|R/W|W|U|W|W|
|EXEC|IRQ||ADDR_MASK|COMMAND||
|4|12|
|W|W|
|FLAGS|DMALEN|
}}
This register controls the state of the NAND interface.
{{regdesc
|EXEC|Write 1: initiate NAND command<br/>Read: NAND interface busy
|IRQ|Set to enable IRQ generation
|ADDR_MASK|Mask of the address bytes to send (10 {{=}} AA, 08 {{=}} BB, ..., 01 {{=}} FF)
|COMMAND|8-bit NAND command
|FLAGS|TBD
|DMALEN|Number of bytes to copy
}}
{| border="1"
{| border="1"