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Hardware/NAND Interface (view source)
Revision as of 03:37, 27 February 2009
, 03:37, 27 February 2009no edit summary
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| armirq = 1
| armirq = 1
}}
}}
+
+{{reglist|NAND Interface}}
+{{rld|0x0d010000 (W)|32|NAND_COMMAND_BITMASK|a bitfield}}
+{{rld|0x80000000|1|NAND_COMMAND_ENABLE|this bit must be set for the command to be considered valid}}
+{{rld|0x1F000000|5|NAND_ADDR_MASK|these bits tell the NAND interface which of the address bytes from NAND_ADDR1/2 should be sent with this command}}
+{{rld|0x00FF0000|8|NAND_COMMAND|this is the actual 8-bit NAND command}}
+{{rld|0x0000F000|4|NAND_COMMAND_FLAGS|tbd}}
+{{rld|0x00000FFF|12|NAND_COMMAND_DMALEN|this tells the DMA engine how many bytes to copy}}
+{{rld|0x0d010000 (R)|32|NAND_STATUS}}
+{{rld|0x0d010004|32|NAND_CONFIG}}
+{{rld|0x0d010008|32|NAND_ADDR1}}
+{{rld|0x0d01000C|32|NAND_ADDR2}}
+{{rld|0x0d010010|32|NAND_DATABUF}}
+{{rld|0x0d010014|32|NAND_ECCBUF}}
+|}
+
{| border="1"
{| border="1"
! base !! function !! offset !! description !! contents/example
! base !! function !! offset !! description !! contents/example