834
edits
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added NAND_CONFIG info
Line 42:
Line 42:
}}
}}
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−{{reg32 | NAND_CONF | addr = 0x0d010004 | hifields = 1 | lofields = 1 |
+{{reg32 | NAND_CONF | addr = 0x0d010004 | hifields = 4 | lofields = 2 |
−|16|
+|4|1|4|8|
−|?|
+|R/W|R/W|R/W|R/W|
−|Unknown||
+|ATTR0|ENABLE|ATTR1|ATTR2||
−|16|
+|8|8|
−|?|
+|R/W|R/W|
−|Unknown|
+|ATTR3|ATTR4|
}}
}}
−This register probably configures certain aspects of the NAND interface (timings?){{check}}. The bit definitions are unknown. This register is written with the values 0x08000000 and 0x4b3e0e7f during initialization.
+This register probably configures certain aspects of the NAND interface (timings?){{check}}.
+{{regdesc
+|ATTR0|Set based on lookup table; set to 3 for 128MB NAND chips, 4 otherwise
+|ENABLE|Set to 1 before first command is sent to NAND, set to 0 when de-initializing the NAND driver.
+|ATTR1|Set based on lookup table; always 0x3
+|ATTR2|Set based on lookup table; always 0x3e
+|ATTR3|Set based on lookup table; always 0x0e
+|ATTR4|Set based on lookup table; always 0x7f
+}}
+When IOS initializes the NAND driver, it turns on the enable bit (writing 0x08000000) and then send the GET CHIP ID command (0x90). Based on the reply, it looks up the correct definitions of the other attributes and pokes them into this register (generally, 0x4b3e0e7f).
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{{reg32 | NAND_ADDR1 | addr = 0x0d010008 | hifields = 1 | lofields = 2 |
{{reg32 | NAND_ADDR1 | addr = 0x0d010008 | hifields = 1 | lofields = 2 |