Changes

}}

}}

{{hwstub}}

{{hwstub}}

Protected memory is always 1 page long (page size is 1024 bytes), and you can specify only 4 protected regions. If the CPU tries to access the protected region in a way that is not allowed, an external interrupt will be raised. Because there are only 4 protected regions, there are a total of 4 possible interrupts which are called MEM_0, MEM_1, MEM_2 and MEM_3.

Protected memory is always 1 page long (page size is 1024 bytes), and you can specify only 4 protected regions. If the CPU tries to access the protected region in a way that is not allowed, an external interrupt will be raised. Because there are only 4 protected regions, there are a total of 4 possible interrupts which are called MEM_0, MEM_1, MEM_2 and MEM_3. Page addresses are calculated with (physical_address >> 10)

== Registers ==

== Registers ==

{{reg32 | MI_PROT_RGN0 | addr = 0x0C004000 | hifields = 1 | lofields = 1 |

{{reg32 | MI_PROT_RGN0 | addr = 0x0C004000 | hifields = 1 | lofields = 1 |

|16  |

|16  |

|R/W |

|R/W |

|Low 16 bits of protected address ||

|Low 16 bits of protected page address ||

|16  |

|16  |

|R/W |

|R/W |

|High 16 bits of protected address |

|High 16 bits of protected page address |

|}}

|}}

{{reg32 | MI_PROT_RGN1 | addr = 0x0C004004 | hifields = 1 | lofields = 1 |

{{reg32 | MI_PROT_RGN1 | addr = 0x0C004004 | hifields = 1 | lofields = 1 |

|16  |

|16  |

|R/W |

|R/W |

|Low 16 bits of protected address ||

|Low 16 bits of protected page address ||

|16  |

|16  |

|R/W |

|R/W |

|High 16 bits of protected address |

|High 16 bits of protected page address |

|}}

|}}

{{reg32 | MI_PROT_RGN2 | addr = 0x0C004008 | hifields = 1 | lofields = 1 |

{{reg32 | MI_PROT_RGN2 | addr = 0x0C004008 | hifields = 1 | lofields = 1 |

|16  |

|16  |

|R/W |

|R/W |

|Low 16 bits of protected address ||

|Low 16 bits of protected page address ||

|16  |

|16  |

|R/W |

|R/W |

|High 16 bits of protected address |

|High 16 bits of protected page address |

|}}

|}}

{{reg32 | MI_PROT_RGN3 | addr = 0x0C00400C | hifields = 1 | lofields = 1 |

{{reg32 | MI_PROT_RGN3 | addr = 0x0C00400C | hifields = 1 | lofields = 1 |

|16  |

|16  |

|R/W |

|R/W |

|Low 16 bits of protected address ||

|Low 16 bits of protected page address ||

|16  |

|16  |

|R/W |

|R/W |

|High 16 bits of protected address |

|High 16 bits of protected page address |

|}}

|}}

}}

}}

{{regsimple | MI_TIMER0 | addr = 0x0C004032 | bits = 32 | access = R/?}}

{{regsimple | MI_TIMER0H | addr = 0x0C004032 | bits = 16 | access = R/?}}

{{regsimple | MI_TIMER1 | addr = 0x0C004036 | bits = 32 | access = R/?}}

{{regsimple | MI_TIMER0L | addr = 0x0C004034 | bits = 16 | access = R/?}}

{{regsimple | MI_TIMER2 | addr = 0x0C00403A | bits = 32 | access = R/?}}

{{regsimple | MI_TIMER1H | addr = 0x0C004036 | bits = 16 | access = R/?}}

{{regsimple | MI_TIMER3 | addr = 0x0C00403E | bits = 32 | access = R/?}}

{{regsimple | MI_TIMER1L | addr = 0x0C004038 | bits = 16 | access = R/?}}

{{regsimple | MI_TIMER4 | addr = 0x0C004042 | bits = 32 | access = R/?}}

{{regsimple | MI_TIMER2H | addr = 0x0C00403A | bits = 16 | access = R/?}}

{{regsimple | MI_TIMER5 | addr = 0x0C004046 | bits = 32 | access = R/?}}

{{regsimple | MI_TIMER2L | addr = 0x0C00403C | bits = 16 | access = R/?}}

{{regsimple | MI_TIMER6 | addr = 0x0C00404A | bits = 32 | access = R/?}}

{{regsimple | MI_TIMER3H | addr = 0x0C00403E | bits = 16 | access = R/?}}

{{regsimple | MI_TIMER7 | addr = 0x0C00404E | bits = 32 | access = R/?}}

{{regsimple | MI_TIMER3L | addr = 0x0C004040 | bits = 16 | access = R/?}}

{{regsimple | MI_TIMER8 | addr = 0x0C004052 | bits = 32 | access = R/?}}

{{regsimple | MI_TIMER4H | addr = 0x0C004042 | bits = 16 | access = R/?}}

{{regsimple | MI_TIMER9 | addr = 0x0C004056 | bits = 32 | access = R/?}}

{{regsimple | MI_TIMER4L | addr = 0x0C004044 | bits = 16 | access = R/?}}

{{regsimple | MI_TIMER5H | addr = 0x0C004046 | bits = 16 | access = R/?}}

{{regsimple | MI_TIMER5L | addr = 0x0C004048 | bits = 16 | access = R/?}}

{{regsimple | MI_TIMER6H | addr = 0x0C00404A | bits = 16 | access = R/?}}

{{regsimple | MI_TIMER6L | addr = 0x0C00404C | bits = 16 | access = R/?}}

{{regsimple | MI_TIMER7H | addr = 0x0C00404E | bits = 16 | access = R/?}}

{{regsimple | MI_TIMER7L | addr = 0x0C004050 | bits = 16 | access = R/?}}

{{regsimple | MI_TIMER8H | addr = 0x0C004052 | bits = 16 | access = R/?}}

{{regsimple | MI_TIMER8L | addr = 0x0C004054 | bits = 16 | access = R/?}}

{{regsimple | MI_TIMER9H | addr = 0x0C004056 | bits = 16 | access = R/?}}

{{regsimple | MI_TIMER9L | addr = 0x0C004058 | bits = 16 | access = R/?}}

{{regdesc

{{regdesc

|Timer|Writing anything to a timer resets it to 0.

|Timer|Writing anything to a timer resets it to 0.