24
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→Register List: fix duplicate interrupt name
Line 41:
Line 41:
|2|1 |1 |1 |1 |3 |3 |1 |1 |1 |1 |
|2|1 |1 |1 |1 |3 |3 |1 |1 |1 |1 |
| |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |
| |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |
−| |ROMDIS |EXT |EXTINT |EXTINTMASK |CS |CLK |TCINT |TCINTMASK |EXTINT |EXTINTMASK ||
+| |ROMDIS |EXT |EXTINT |EXTINTMASK |CS |CLK |TCINT |TCINTMASK |EXIINT |EXIINTMASK ||
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This register at least controls the boot0 memory mapping and DSK PLL source.
This register at least controls the boot0 memory mapping and DSK PLL source.
Line 71:
Line 71:
|TCINTMASK|Transfer complete interrupt mask (1 - enable, 0 - disable).
|TCINTMASK|Transfer complete interrupt mask (1 - enable, 0 - disable).
Interrupt masking prevents the interrupt from being sent to the main processor, but does not affect the assertion of TCINT
Interrupt masking prevents the interrupt from being sent to the main processor, but does not affect the assertion of TCINT
−|EXTINT|Interrupt Status
+|EXIINT|Interrupt Status
* When read 1 or 0 indicates if interrupt is requested
* When read 1 or 0 indicates if interrupt is requested
* When 1 is written to this register, it clears the interrupt
* When 1 is written to this register, it clears the interrupt
−|EXTINTMASK|EXI interrupt mask (1 - enable, 0 - disable)
+|EXIINTMASK|EXI interrupt mask (1 - enable, 0 - disable)
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