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Register HW_IPC_ARMCTRL can only be accessed by the Starlet. The other three registers can be accessed by both CPUs.
Register HW_IPC_ARMCTRL can only be accessed by the Starlet. The other three registers can be accessed by both CPUs.
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=== IOS flag protocol ===
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{{regdesc
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|X1|Execute command: a new pointer is available ''in HW_IPC_PPCCTRL''
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|Y2|Command acknowledge
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|Y1|Command executed and reply available in ''HW_IPC_ARMMSG''
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|X2|Relaunch
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}}
== Register List ==
== Register List ==
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}}
}}
This register exposes the Broadway side of the IPC control. Flags X1 and X2 may be freely set/cleared. Flags Y1 and Y2 can be read and cleared (by writing one), and can optionally generate IRQ #30.
This register exposes the Broadway side of the IPC control. Flags X1 and X2 may be freely set/cleared. Flags Y1 and Y2 can be read and cleared (by writing one), and can optionally generate IRQ #30.
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===IOS usage===
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{{regdesc
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|X1|Execute command: a new pointer is available ''in HW_IPC_PPCCTRL''
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|Y2|Command acknowledge
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|Y1|Command executed and reply available in ''HW_IPC_ARMMSG''
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|X2|Relaunch
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}}
----
----
{{regsimple | HW_IPC_ARMMSG | addr = 0x0d800008 | bits = 32 | access = R/W }}
{{regsimple | HW_IPC_ARMMSG | addr = 0x0d800008 | bits = 32 | access = R/W }}