Changes

Hardware/Memory Controller (view source)

Revision as of 05:17, 29 March 2020

8,221 bytes added , 05:17, 29 March 2020

add SEQ/BIST/DPERF listing from 100J/121J

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* For the DDR SEQ registers, MEM_SEQ_ADDR and MEM_SEQ_DATA

* For the DDR BIST, MEM_BIST_ADDR and MEM_BIST_DATA

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* For the DPERF registers, presumably MEM_PERF and MEM_PERF_READ are involved {{check}}

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* MEM_ARB_EXADDR and MEM_ARB_EXCMD might hint at the existence of some other yet-undocumented register space (perhaps for AHB arbitration) {{check}}

Although the memory controller registers are actually mapped and available to ARM starting at 0x0d8b4200, some [all?] of the indirect accesses are

performed starting with another pair in the [[Hardware/Memory_Interface|Memory Interface registers]].

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~~''Note: MEM_ARB_EXADDR and MEM_ARB_EXCMD at the end of the register space may also indicate an additional set of indirectly-accessible registers.''~~

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''Note: These registers are NOT mapped into memory.''

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''Note: These registers are NOT mapped into memory.''

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''Note: These registers are NOT mapped into memory.''

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|}

Metaconstruct

33

edits

Changes

Hardware/Memory Controller (view source)

Revision as of 05:17, 29 March 2020

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