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}}
−{{Infobox MMIO
−| title = SEQ
−| arm = Full
−| ppc = ???
−| base = N/A
−| len = ???
−| bits = 16
−}}
−{{Infobox MMIO
−| title = BIST
−| arm = Full
−| ppc = ???
−| base = N/A
−| len = ???
−| bits = 16
−}}
−{{Infobox MMIO
−| title = PERF
−| arm = Full
−| ppc = ???
−| base = N/A
−| len = ???
−| bits = 16
−}}
−{{Infobox MMIO
−| title = ARB_EX (?)
−| arm = ???
−| ppc = ???
−| base = ???
−| len = ???
−| bits = ???
+
+== DDR SEQ Register Space ==+== DDR BIST Register Space ==+== DDR PERF Register Space ==+
| len = 0xcc (?)
| len = 0xcc (?)
| bits = 16
| bits = 16
−}}
}}
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The IOS[58] kernel also exposes syscall 0x57 for writing to this register space, which only appears to be used by the STM module.
The IOS[58] kernel also exposes syscall 0x57 for writing to this register space, which only appears to be used by the STM module.
−Some of these register banks (SEQ/BIST/PERF) are not directly mapped into memory, but are instead accessed using a corresponding pair of registers.
+Some of these register banks (SEQ/BIST/PERF) are not directly mapped into memory, but are instead accessed using a corresponding pair of registers:
−Although the memory controller registers are actually mapped and available to ARM starting at 0x0d8b4200, some [all?] of these indirect accesses are
+* For the DDR SEQ registers, MEM_SEQ_ADDR and MEM_SEQ_DATA
+* For the DDR BIST, MEM_BIST_ADDR and MEM_BIST_DATA
+Although the memory controller registers are actually mapped and available to ARM starting at 0x0d8b4200, some [all?] of the indirect accesses are
performed starting with another pair in the [[Hardware/Memory_Interface|Memory Interface registers]].
performed starting with another pair in the [[Hardware/Memory_Interface|Memory Interface registers]].
+
+''Note: MEM_ARB_EXADDR and MEM_ARB_EXCMD at the end of the register space may also indicate an additional set of indirectly-accessible registers.''
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|}
|}
−= DDR SEQ Register Space =
+{{Infobox MMIO
+| title = SEQ
+| arm = Full
+| ppc = ???
+| base = N/A
+| len = ???
+| bits = 16
+}}
+''Note: These registers are NOT mapped into memory.''
+{{reglist|DDR SEQ Registers}}
+|}
−= DDR BIST Register Space =
+{{Infobox MMIO
+| title = BIST
+| arm = Full
+| ppc = ???
+| base = N/A
+| len = ???
+| bits = 16
+}}
+''Note: These registers are NOT mapped into memory.''
+{{reglist|DDR BIST Registers}}
+|}
−= DDR PERF Register Space =
+{{Infobox MMIO
+| title = PERF
+| arm = Full
+| ppc = ???
+| base = N/A
+| len = ???
+| bits = 16
+}}
+''Note: These registers are NOT mapped into memory.''
+{{reglist|DDR PERF Registers}}
+|}