Hardware/Broadway

PPC redirects here. For the SDK library, see PPC (SDK)

The Broadway is the main processor on the Wii, and runs games. Games have the entire processor to themselves; IOS runs on the Starlet.

Specifications

• IBM 'Broadway' 90 nm based on IBM's PowerPC architecture.
• Runs at a speed of 729 MHz. Maximum Bandwidth is 1.9 GB/s.
• Bus to main memory: 243 MHz, 64 bits (maximum bandwidth: 1.9 GB/s)
• 32 KB 8-way set-associative L1 instruction cache
• 32 KB 8-way set-associative L1 data cache (can set up 16-kilobyte data scratch pad)
• Superscalar microprocessor with six execution units (floating-point unit, branching unit, system register unit, load/store unit, two integer units)
• DMA unit (15-entry DMA request queue) used by 16-kilobyte data scratch pad
• Write-gather buffer for writing graphics command lists to the graphics chip
• Onboard 256-kilobyte 2-way set-associative L2 integrated cache
• Two, 32-bit integer units (IU)
• One floating point unit (FPU) (supports single precision (32-bit) and double precision (64-bit))
• The FPU supports paired single floating point (FP/PS)
• The FPU supports paired single multiply add (ps_madd). Most FP/PS instructions can be issued in each cycle and completed in three cycles.
• Fixed-point to floating-point conversion can be performed at the same time as FPU register load and store, with no loss in performance.
• The branch unit supports static branch prediction and dynamic branch prediction.
• When an instruction is stalled on data, the next instruction can be issued and executed. All instructions maintain program logic and will complete in the correct program order.
• Supports three L2 cache fetch modes: 32-Byte, 64-Byte, and 128-Byte.
• Supports these bus pipeline depth levels: level 2, level 3, and level 4.

Reference Information: Broadway is upward compatible with Nintendo GameCube’s CPU (Gekko).

• Broadway CPU version is 87102, Gekko is 83410. Source: http://forum.wiibrew.org/viewtopic.php?t=210
• Information about its registers is available

EXI boot code

The Broadway boots from fff00100, which is where the EXI boot registers are mapped; there is space for 16 instructions, and they can be initialized by the Starlet by writing the instructions to 0d806840.

IOS's function to initialize the EXI buffer has 2 default boot vectors depending on the parameters, but a custom boot vector is used by the IOS_StartPPC syscall.

Default vector (with HID4 initialization)

fff00100    7c 63 1a 78    xor   r3, r3, r3
fff00104    64 63 d7 b0    oris  r3, r3, 0xd7b0
fff00108    7c 73 fb a6    mtspr HID4, r3
fff0010c    4c 00 01 2c    isync
fff00110    3c 40 00 00    lis   r2, 0x0
fff00114    60 42 01 00    ori   r2, r2, 0x100
fff00118    7c 5a 03 a6    mtspr SRR0, r2
fff0011c    38 a0 00 00    li    r5, 0
fff00120    7c bb 03 a6    mtspr SRR1, r5
fff00124    4c 00 00 64    rfi
fff00128    60 00 00 00    nop
fff0012c    60 00 00 00    nop
fff00130    60 00 00 00    nop

Default vector (without HID4 initialization)

fff00100    7c 63 1a 78    xor   r3, r3, r3
fff00104    7c 73 fb a6    mtspr HID4, r3
fff00108    4c 00 01 2c    isync
fff0010c    3c 40 00 00    lis   r2, 0
fff00110    60 42 01 00    ori   r2, r2, 0x100
fff00114    7c 5a 03 a6    mtspr SRR0, r2
fff00118    38 a0 00 00    li    r5, 0
fff0010c    7c bb 03 a6    mtspr SRR1, r5
fff00120    4c 00 00 64    rfi
fff00124    60 00 00 00    nop
fff00128    60 00 00 00    nop
fff0012c    60 00 00 00    nop

IOS_StartPPC vector

fff00100    3c 60 00 00    lis   r3, 0
fff00104    60 63 34 00    ori   r3, r3, 0x3400
fff00108    7c 7a 03 a6    mtspr SRR0, r3
fff0010c    38 60 00 00    li    r3, 0
fff00110    7c 7b 03 a6    mtspr SRR1, r3
fff00114    4c 00 00 64    rfi