533
edits
Changes
Hardware/External Interface (view source)
Revision as of 14:12, 25 September 2022
, 14:12, 25 September 2022→Registry List
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=== Parameter Register ===
=== Parameter Register ===
−{{reg32 | EXIX_CSR | addr = | hifields = 1 | lofields = 9 |
+{{reg32 | EXIX_CSR | addr = | hifields = 1 | lofields = 11 |
|16|
|16|
| |
| |
| ||
| ||
|2|1 |1 |1 |1 |3 |3 |1 |1 |1 |1 |
|2|1 |1 |1 |1 |3 |3 |1 |1 |1 |1 |
+| |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |
+| |ROMDIS |EXT |EXTINT |EXTINTMASK |CS |CLK |TCINT |TCINTMASK |EXTINT |EXTINTMASK ||
}}
}}
This register at least controls the boot0 memory mapping and DSK PLL source.
This register at least controls the boot0 memory mapping and DSK PLL source.
{{regdesc
{{regdesc
−|ROMDIS|(EXI0 only) 1: rom de-scramble logic disabled (*1)
+|ROMDIS|on GC it masked the ipl, Unknown purpose on the wii
|EXT|Device Connected Bit (R) 1 if a device is connected on the specific channel
|EXT|Device Connected Bit (R) 1 if a device is connected on the specific channel
|EXTINT|External Insertion Interrupt Status
|EXTINT|External Insertion Interrupt Status
+This interrupt indicates than an external EXI device has been removed from channel x.
+To check whether the device has been inserted or removed, check the EXICPR bit. When this bit is set, the channel's expansion EXI interface outputs go to high.
* When read 1 or 0 indicates if interrupt is requested
* When read 1 or 0 indicates if interrupt is requested
* When 1 is written to this register, it clears the interrupt
* When 1 is written to this register, it clears the interrupt
|EXTINTMASK|EXT Interrupt Mask (1 - enable, 0 - disable) (*5)
|EXTINTMASK|EXT Interrupt Mask (1 - enable, 0 - disable) (*5)
−|CS|devices selected on this channel, each bit selecting one device. (*)
+|CS|devices selected on this channel, each bit selecting one device.
+Only one of these three bits can be set to signify which device number has been selected on a specific channel.
|CLK|used frequency
|CLK|used frequency
<source>
<source>
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* When read 1 or 0 indicates if interrupt is requested
* When read 1 or 0 indicates if interrupt is requested
* When 1 is written to this register, it clears the interrupt
* When 1 is written to this register, it clears the interrupt
−|TCINTMASK|Transfer complete interrupt mask (1 - enable, 0 - disable) (*2)
+|TCINTMASK|Transfer complete interrupt mask (1 - enable, 0 - disable).
+Interrupt masking prevents the interrupt from being sent to the main processor, but does not affect the assertion of TCINT
|EXTINT|Interrupt Status
|EXTINT|Interrupt Status
* When read 1 or 0 indicates if interrupt is requested
* When read 1 or 0 indicates if interrupt is requested