533
edits
Changes
Jump to navigation
Jump to search
m
Hardware/External Interface (view source)
Revision as of 14:56, 25 September 2022
, 14:56, 25 September 2022→Registry List
Line 16:
Line 16:
=== Parameter Register ===+
−
== Registry List ==
== Registry List ==
{{reglist|EXI}}
{{reglist|EXI}}
−{{rla|0x0d806800|32|EXI0_CSR|EXI Channel 0 Parameter Register (Status?)}}
+{{rla|0x0d806800|32|EXI_CSR|EXI Channel 0 Parameter Register (Status?)}}
−{{rla|0x0d806800|32|EXI0_MAR|EXI Channel 0 DMA Start Address}}
+{{rla|0x0d806800|32|EXI_MAR|EXI Channel 0 DMA Start Address}}
−{{rla|0x0d806800|32|EXI0_LENGTH|EXI EXI Channel 0 DMA Transfer Length}}
+{{rla|0x0d806800|32|EXI_LENGTH|EXI EXI Channel 0 DMA Transfer Length}}
−{{rla|0x0d806800|32|EXI0_CR|EXI Channel 0 Control Register}}
+{{rla|0x0d806800|32|EXI_CR|EXI Channel 0 Control Register}}
−{{rla|0x0d806810|32|EXI0_DATA|EXI Channel 0 Immediate Data}}
+{{rla|0x0d806810|32|EXI_DATA|EXI Channel 0 Immediate Data}}
−{{rla|0x0d806814|32|EXI1_CSR|EXI Channel 1 Parameter Register (Status?)}}
+{{rla|0x0d806814|32|EXI_CSR|EXI Channel 1 Parameter Register (Status?)}}
−{{rla|0x0d806818|32|EXI1_MAR|EXI Channel 1 DMA Start Address}}
+{{rla|0x0d806818|32|EXI_MAR|EXI Channel 1 DMA Start Address}}
−{{rla|0x0d80681c|32|EXI1_LENGTH|EXI EXI Channel 1 DMA Transfer Length}}
+{{rla|0x0d80681c|32|EXI_LENGTH|EXI EXI Channel 1 DMA Transfer Length}}
−{{rla|0x0d806820|32|EXI0_CR|EXI Channel 1 Control Register (Status?)}}
+{{rla|0x0d806820|32|EXI_CR|EXI Channel 1 Control Register (Status?)}}
−{{rla|0x0d806824|32|EXI0_DATA|EXI Channel 1 Immediate Data}}
+{{rla|0x0d806824|32|EXI_DATA|EXI Channel 1 Immediate Data}}
−{{rla|0x0d806828|32|EXI2_CSR|EXI Channel 2 Parameter Register (Status?)}}
+{{rla|0x0d806828|32|EXI_CSR|EXI Channel 2 Parameter Register (Status?)}}
−{{rla|0x0d80682c|32|EXI2_MAR|EXI Channel 2 DMA Start Address}}
+{{rla|0x0d80682c|32|EXI_MAR|EXI Channel 2 DMA Start Address}}
−{{rla|0x0d806830|32|EXI2_LENGTH|EXI EXI Channel 2 DMA Transfer Length}}
+{{rla|0x0d806830|32|EXI_LENGTH|EXI EXI Channel 2 DMA Transfer Length}}
−{{rla|0x0d806834|32|EXI2_CR|EXI Channel 2 Control Register (Status?)}}
+{{rla|0x0d806834|32|EXI_CR|EXI Channel 2 Control Register (Status?)}}
−{{rla|0x0d806838|32|EXI2_DATA|EXI Channel 2 Immediate Data}}
+{{rla|0x0d806838|32|EXI_DATA|EXI Channel 2 Immediate Data}}
|}
|}
−{{reg32 | EXI_CSR| addr = | hifields = 1 | lofields = 11 |
−{{reg32 | EXIX_CSR | addr = | hifields = 1 | lofields = 11 |
|16|
|16|
| |
| |
Line 76:
Line 74:
|EXTINTMASK|EXI interrupt mask (1 - enable, 0 - disable)
|EXTINTMASK|EXI interrupt mask (1 - enable, 0 - disable)
}}
}}
+
+{{reg32 | EXIMAR| addr = | hifields = 2 | lofields = 2 |
+|5|11 |
+| |R/W |
+| |Data ||
+|11 |5|
+|R/W | |
+|Data | ||
+}}
+Physical Startaddress for DMA transfer. Must be aligned to 32 byte boundary.
+
+
+{{reg32 | EXI_LENGTH| addr = | hifields = 2 | lofields = 2 |
+|5|11 |
+| |R/W |
+| |Data ||
+|11 |5|
+|R/W | |
+|Data | ||
+}}
+Size of DMA transfer data in bytes. bits 0-4 are always zero (which means the size is 32 byte aligned)
+
+
+{{reg32 | EXI_CR| addr = | hifields = 1 | lofields = 5 |
+|16 |
+| |
+| ||
+|10 |2 |2 |1 |1 |
+| |TLEN|RW |DMA |TSTART |
+| |R/W |R/W|R/W |R/W ||
+}}
+{{regdesc
+|TLEN|(data length-1) for immediate mode
+<source>
+00 = 1 byte
+01 = 2 byte
+10 = 3 byte
+11 = 4 byte
+</source>
+|RW|transfer type
+<source>
+00 = read
+01 = write
+10 = read and write, invalid for DMA
+11 = undefined
+</source>
+|DMA|transfer mode (0 - immediate, 1 - DMA)
+|TSTART|set, to start transfer. will be cleared after transfer completed.
+}}
+
+
+{{reg32 | EXI_DATA| addr = | hifields = 1 | lofields = 1 |
+|16 |
+|R/W |
+|Data||
+|16 |
+|R/W |
+|Data||
+}}
+Data for read / write immediate operations (up to 4 bytes long).
== EXI boot vector ==
== EXI boot vector ==