In memory of Ben “bushing” Byer, who passed away on Monday, February 8th, 2016.

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Hardware/External Interface (view source)

Revision as of 14:00, 25 September 2022

1,350 bytes added ,  14:00, 25 September 2022
→‎Registry List
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== Registry List ==
 
== Registry List ==
 
{{reglist|EXI}}
 
{{reglist|EXI}}
−
{{rla|0x0d806800|32|EXI0_CSR|EXI Channel 0 Parameter Register}}
+
{{rla|0x0d806800|32|EXI0_CSR|EXI Channel 0 Parameter Register (Status?)}}
 
{{rla|0x0d806800|32|EXI0_MAR|EXI Channel 0 DMA Start Address}}
 
{{rla|0x0d806800|32|EXI0_MAR|EXI Channel 0 DMA Start Address}}
 
{{rla|0x0d806800|32|EXI0_LENGTH|EXI EXI Channel 0 DMA Transfer Length}}
 
{{rla|0x0d806800|32|EXI0_LENGTH|EXI EXI Channel 0 DMA Transfer Length}}
 
{{rla|0x0d806800|32|EXI0_CR|EXI Channel 0 Control Register}}
 
{{rla|0x0d806800|32|EXI0_CR|EXI Channel 0 Control Register}}
 
{{rla|0x0d806810|32|EXI0_DATA|EXI Channel 0 Immediate Data}}
 
{{rla|0x0d806810|32|EXI0_DATA|EXI Channel 0 Immediate Data}}
−
{{rla|0x0d806814|32|EXI1_CSR|EXI Channel 1 Parameter Register}}
+
{{rla|0x0d806814|32|EXI1_CSR|EXI Channel 1 Parameter Register (Status?)}}
 
{{rla|0x0d806818|32|EXI1_MAR|EXI Channel 1 DMA Start Address}}
 
{{rla|0x0d806818|32|EXI1_MAR|EXI Channel 1 DMA Start Address}}
 
{{rla|0x0d80681c|32|EXI1_LENGTH|EXI EXI Channel 1 DMA Transfer Length}}
 
{{rla|0x0d80681c|32|EXI1_LENGTH|EXI EXI Channel 1 DMA Transfer Length}}
−
{{rla|0x0d806820|32|EXI0_CR|EXI Channel 1 Control Register}}
+
{{rla|0x0d806820|32|EXI0_CR|EXI Channel 1 Control Register (Status?)}}
 
{{rla|0x0d806824|32|EXI0_DATA|EXI Channel 1 Immediate Data}}
 
{{rla|0x0d806824|32|EXI0_DATA|EXI Channel 1 Immediate Data}}
−
{{rla|0x0d806828|32|EXI2_CSR|EXI Channel 2 Parameter Register}}
+
{{rla|0x0d806828|32|EXI2_CSR|EXI Channel 2 Parameter Register (Status?)}}
 
{{rla|0x0d80682c|32|EXI2_MAR|EXI Channel 2 DMA Start Address}}
 
{{rla|0x0d80682c|32|EXI2_MAR|EXI Channel 2 DMA Start Address}}
 
{{rla|0x0d806830|32|EXI2_LENGTH|EXI EXI Channel 2 DMA Transfer Length}}
 
{{rla|0x0d806830|32|EXI2_LENGTH|EXI EXI Channel 2 DMA Transfer Length}}
−
{{rla|0x0d806834|32|EXI2_CR|EXI Channel 2 Control Register}}
+
{{rla|0x0d806834|32|EXI2_CR|EXI Channel 2 Control Register (Status?)}}
 
{{rla|0x0d806838|32|EXI2_DATA|EXI Channel 2 Immediate Data}}
 
{{rla|0x0d806838|32|EXI2_DATA|EXI Channel 2 Immediate Data}}
 
|}
 
|}
 +
 +
=== Parameter Register ===
 +
 +
{{reg32 | EXIX_CSR | addr = | hifields = 1 | lofields = 9 |
 +
|16|
 +
| |
 +
|          ||
 +
|2|1        |1    |1      |1          |3  |3  |1    |1        |1      |1          |
 +
}}
 +
This register at least controls the boot0 memory mapping and DSK PLL source.
 +
{{regdesc
 +
|ROMDIS|(EXI0 only) 1: rom de-scramble logic disabled (*1)
 +
|EXT|Device Connected Bit (R) 1 if a device is connected on the specific channel
 +
|EXTINT|External Insertion Interrupt Status
 +
* When read 1 or 0 indicates if interrupt is requested
 +
* When 1 is written to this register, it clears the interrupt
 +
|EXTINTMASK|EXT Interrupt Mask (1 - enable, 0 - disable) (*5)
 +
|CS|devices selected on this channel, each bit selecting one device. (*)
 +
|CLK|used frequency
 +
<source>
 +
000 = 1MHz
 +
001 = 2MHz
 +
010 = 4MHz
 +
011 = 8MHz
 +
100 = 16MHz
 +
101 = 32MHz
 +
110 = reserved
 +
111 = reserved
 +
</source>
 +
|TCINT|Transfer Complete Interrupt Status
 +
* When read 1 or 0 indicates if interrupt is requested
 +
* When 1 is written to this register, it clears the interrupt
 +
|TCINTMASK|Transfer complete interrupt mask (1 - enable, 0 - disable) (*2)
 +
|EXTINT|Interrupt Status
 +
* When read 1 or 0 indicates if interrupt is requested
 +
* When 1 is written to this register, it clears the interrupt
 +
|EXTINTMASK|EXI interrupt mask (1 - enable, 0 - disable)
 +
}}
    
== EXI boot vector ==
 
== EXI boot vector ==
Retrieved from "https://wiibrew.org/wiki/Special:MobileDiff/118286"

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