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Hardware/Memory Controller (view source)
Revision as of 09:48, 8 November 2019
, 09:48, 8 November 2019no edit summary
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These registers contain various settings relevant to configuring system memory (and perhaps some aspects of the AHB).
These registers contain various settings relevant to configuring system memory (and perhaps some aspects of the AHB).
[[boot1]] seems responsible for initially configuring a lot of these registers during the boot process - most likely for setting the DDR memory timings.
[[boot1]] seems responsible for initially configuring a lot of these registers during the boot process - most likely for setting the DDR memory timings.
−The IOS[58] kernel exposes syscall 0x57 for writing to this register space, which only appears to be used by the STM module.
+In general, IOS (including BC/MIOS) seem to interact with these early when booting.
+The IOS[58] kernel also exposes syscall 0x57 for writing to this register space, which only appears to be used by the STM module.
Some of these register banks (SEQ/BIST/PERF) are not directly mapped into memory, but are instead accessed using a corresponding pair of registers.
Some of these register banks (SEQ/BIST/PERF) are not directly mapped into memory, but are instead accessed using a corresponding pair of registers.