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Hardware/Memory Controller (view source)
Revision as of 03:12, 8 November 2019
, 03:12, 8 November 2019Started description of Memory Controller interface
{{Infobox MMIO
| title = Memory Controller
| arm = Full
| ppc = ???
| base = 0x0d8b4200
| len = 0xcc (?)
| bits = 16
}}
{{Infobox MMIO
| title = SEQ
| arm = Full
| ppc = ???
| base = N/A
| len = ???
| bits = 16
}}
{{Infobox MMIO
| title = BIST
| arm = Full
| ppc = ???
| base = N/A
| len = ???
| bits = 16
}}
{{Infobox MMIO
| title = PERF
| arm = Full
| ppc = ???
| base = N/A
| len = ???
| bits = 16
}}
{{Infobox MMIO
| title = ARB_EX (?)
| arm = ???
| ppc = ???
| base = ???
| len = ???
| bits = ???
}}
These registers contain various settings relevant to configuring system memory (and perhaps some aspects of the AHB).
[[boot1]] seems responsible for initially configuring a lot of these registers during the boot process - most likely for setting the DDR memory timings.
The IOS[58] kernel exposes syscall 0x57 for writing to this register space, which only appears to be used by the STM module.
Some of these register banks (SEQ/BIST/PERF) are not directly mapped into memory, but are instead accessed using a corresponding pair of registers.
Although the memory controller registers are actually mapped and available to ARM starting at 0x0d8b4200, some [all?] of these indirect accesses are
performed starting with another pair in the [[Hardware/Memory_Interface|Memory Interface registers]].
{{reglist|Memory Controller Base Registers}}
{{rld|0x0d8b4200|16|MEM_COMPAT||}}
{{rld|0x0d8b4202|16|MEM_PROT_REG||}}
{{rld|0x0d8b4204|16|MEM_PROT_SPL|SPL (?) protection enabled/disable|}}
{{rld|0x0d8b4206|16|MEM_PROT_SPL_BASE|SPL (?) protection base address|}}
{{rld|0x0d8b4208|16|MEM_PROT_SPL_END|SPL (?) protection end address|}}
{{rld|0x0d8b420a|16|MEM_PROT_DDR|DDR protection enable/disable|}}
{{rld|0x0d8b420c|16|MEM_PROT_DDR_BASE|DDR protection base address|}}
{{rld|0x0d8b420e|16|MEM_PROT_DDR_END|DDR protection end address|}}
{{rld|0x0d8b4210|16|MEM_COLSEL||}}
{{rld|0x0d8b4212|16|MEM_ROWSEL||}}
{{rld|0x0d8b4214|16|MEM_BANKSEL||}}
{{rld|0x0d8b4216|16|MEM_RANKSEL||}}
{{rld|0x0d8b4218|16|MEM_COLMSK||}}
{{rld|0x0d8b421a|16|MEM_ROWMSK||}}
{{rld|0x0d8b421c|16|MEM_BANKMSK||}}
{{rld|0x0d8b421e|16|MEM_PROT_SPL_ERR||}}
{{rld|0x0d8b4220|16|MEM_PROT_DDR_ERR||}}
{{rld|0x0d8b4222|16|MEM_PROT_SPL_MSK||}}
{{rld|0x0d8b4224|16|MEM_PROT_DDR_MSK||}}
{{rld|0x0d8b4226|16|MEM_RFSH||}}
{{rld|0x0d8b4228|16|MEM_AHMFLUSH|AHB flush request|}}
{{rld|0x0d8b422a|16|MEM_AHMFLUSH_ACK|AHB flush request acknowledgment|}}
{{rld|0x0d8b4268|16|MEM_SEQRD_HWM||}}
{{rld|0x0d8b426a|16|MEM_SEQWR_HWM||}}
{{rld|0x0d8b426c|16|MEM_SEQCMD_HWM||}}
{{rld|0x0d8b426e|16|MEM_CPUAHM_WR_T||}}
{{rld|0x0d8b4270|16|MEM_DMAAHM_WR_T||}}
{{rld|0x0d8b4272|16|MEM_DMAAHM0_WR_T||}}
{{rld|0x0d8b4274|16|MEM_DMAAHM1_WR_T||}}
{{rld|0x0d8b4276|16|MEM_PI_WR_T||}}
{{rld|0x0d8b4278|16|MEM_PE_WR_T||}}
{{rld|0x0d8b427a|16|MEM_IO_WR_T||}}
{{rld|0x0d8b427c|16|MEM_DSP_WR_T||}}
{{rld|0x0d8b427e|16|MEM_ACC_WR_T||}}
{{rld|0x0d8b4280|16|MEM_ARB_MAXWR||}}
{{rld|0x0d8b4282|16|MEM_ARB_MINRD||}}
{{rld|0x0d8b4284|16|MEM_PROF_CPUAHM||}}
{{rld|0x0d8b4286|16|MEM_PROF_CPUAHM0||}}
{{rld|0x0d8b4288|16|MEM_PROF_DMAAHM||}}
{{rld|0x0d8b428a|16|MEM_PROF_DMAAHM0||}}
{{rld|0x0d8b428c|16|MEM_PROF_DMAAHM1||}}
{{rld|0x0d8b428e|16|MEM_PROF_PI||}}
{{rld|0x0d8b4290|16|MEM_PROF_VI||}}
{{rld|0x0d8b4292|16|MEM_PROF_IO||}}
{{rld|0x0d8b4294|16|MEM_PROF_DSP||}}
{{rld|0x0d8b4296|16|MEM_PROF_TC||}}
{{rld|0x0d8b4298|16|MEM_PROF_CP||}}
{{rld|0x0d8b429a|16|MEM_PROF_ACC||}}
{{rld|0x0d8b429c|16|MEM_RDPR_CPUAHM||}}
{{rld|0x0d8b429e|16|MEM_RDPR_CPUAHM0||}}
{{rld|0x0d8b42a0|16|MEM_RDPR_DMAAHM||}}
{{rld|0x0d8b42a2|16|MEM_RDPR_DMAAHM0||}}
{{rld|0x0d8b42a4|16|MEM_RDPR_DMAAHM1||}}
{{rld|0x0d8b42a6|16|MEM_RDPR_PI||}}
{{rld|0x0d8b42a8|16|MEM_RDPR_VI||}}
{{rld|0x0d8b42aa|16|MEM_RDPR_IO||}}
{{rld|0x0d8b42ac|16|MEM_RDPR_DSP||}}
{{rld|0x0d8b42ae|16|MEM_RDPR_TC||}}
{{rld|0x0d8b42b0|16|MEM_RDPR_CP||}}
{{rld|0x0d8b42b2|16|MEM_RDPR_ACC||}}
{{rld|0x0d8b42b4|16|MEM_ARB_MAXRD||}}
{{rld|0x0d8b42b6|16|MEM_ARB_MISC||}}
{{rld|0x0d8b42b8|16|MEM_ARAM_EMUL|"ARAM Emulation" (?)|}}
{{rld|0x0d8b42ba|16|MEM_WRMUX||}}
{{rld|0x0d8b42bc|16|MEM_PERF||}}
{{rld|0x0d8b42be|16|MEM_PERF_READ||}}
{{rld|0x0d8b42c0|16|MEM_ARB_EXADDR||}}
{{rld|0x0d8b42c2|16|MEM_ARB_EXCMD||}}
{{rld|0x0d8b42c4|16|MEM_SEQ_DATA|Data from read (or for pending write) on DDR SEQ|}}
{{rld|0x0d8b42c6|16|MEM_SEQ_ADDR|Offset for access on DDR SEQ register space|}}
{{rld|0x0d8b42c8|16|MEM_BIST_DATA|Data from read (or for pending write) on DDR BIST|}}
{{rld|0x0d8b42ca|16|MEM_BIST_ADDR|Offset for access on DDR BIST register space|}}
|}
== DDR SEQ Register Space ==
== DDR BIST Register Space ==
== DDR PERF Register Space ==