Hardware/DSP

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DSP
Access
BroadwayFull
StarletNone
Registers
Base0x0c005000
Length0x200
Access size16/32 bits
Byte orderBig Endian
IRQs
Broadway6
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Contents

DSP Interface

DSP_MAILBOX_IN_H (0xCC005000)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W R/W
Field Set Data
Field Description
Set This must be set for the DSP to accept the data.
Data This, combined with the Data in DSP_MAILBOX_IN_L is the data being sent to the DSP.

DSP_MAILBOX_IN_L (0xCC005002)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W
Field Data
Field Description
Data This, combined with the Data in DSP_MAILBOX_IN_H is the data being sent to the DSP.


DSP_MAILBOX_OUT_H (0xCC005004)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R R
Field Set Data
Field Description
Set This must be set for the data to be valid.
Data This, combined with the Data in DSP_MAILBOX_OUT_L is the data being sent from the DSP.

DSP_MAILBOX_OUT_L (0xCC005006)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R
Field Data
Field Description
Data This, combined with the Data in DSP_MAILBOX_OUT_H is the data being sent from the DSP.


Control Register

This register holds states for all of the interfaces exposed by this register block.

DSP_CONTROL_STATUS (0xCC00500A)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access U W W W W R/W W R/W W R/W R/W R/W R/W
Field Reset  ? DMAINT DMAINTMSK DSPINT ARINTMSK ARINT AIDINTMSK AIDINT HALT PIINT RES
Field Description
Reset Resets the DSP?
DMAINT DSP DMA Interrupt Status
DMAINTMSK DSP Interrupt Mask
DSPINT DSP Interrupt Status. When read, set means Interrupt is active. Clear is no interrupts. Writing 0 does nothing, while writing 1 clears interrupt.
ARINTMSK ARAM Interrupt Mask
ARINT ARAM Interrupt Status. When read, set means Interrupt is active. Clear is no interrupts. Writing 0 does nothing, while writing 1 clears interrupt.
AIDINTMSK AI Interrupt Mask
AIDINT AI Interrupt Status. When read, set means Interrupt is active. Clear is no interrupts. Writing 0 does nothing, while writing 1 clears interrupt.
HALT Halt DSP? When set, the DSP will halt. When cleared, the DSP will resume.
PIINT DSP Interrupt Assertion? Setting asserts the DSP Interrupt.
RES Writing 1 resets the DSP.


ARAM Interface

DSP_AR_SIZE (0xCC005012)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/? R/W R/W R/W
Field  ?  ? Size CAS
Field Description
? Unknown
? Unknown - set just before writing DSP bootstrap ucode into ARAM. Presumably somehow maps lower ARAM into DSP IRAM space.
Size Seems to set the addressing mode of ARAM controller (for accessing expansion ARAM, etc). Seems to be logically part of DSP_AR_MODE (TODO)
CAS CAS Latency. Defaults to 3 by ARAM controller, but can be set by CPU to 2 as well.


DSP_AR_MODE (0xCC005016)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access  ?/W R/?
Field  ? ARAM_NORM
Field Description
? Some ARAM mode settings. Needs investigation.
ARAM_NORM ARAM Controller sets this flag after it has finished initializing.


DSP_AR_REFRESH (0xCC00501A)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W
Field Refresh
Field Description
Refresh Sets the ARAM refresh rate (in MHz?). Refreshing SDRAM banks is required for data retention.


DSP_AR_DMA_MMADDR_H (0xCC005020)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W
Field MMADDR
Field Description
MMADDR The High half-word of the DMA starting location in Main Memory.

DSP_AR_DMA_MMADDR_L (0xCC005022)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W
Field MMADDR
Field Description
MMADDR The Low half-word of the DMA starting location in Main Memory. The lower 5 bits are hard-wired to 0, effectively performing 32 byte alignment.

DSP_AR_DMA_ARADDR_H (0xCC005024)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W
Field ARADDR
Field Description
ARADDR The High half-word of the DMA starting location in ARAM.

DSP_AR_DMA_ARADDR_L (0xCC005026)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W
Field ARADDR
Field Description
ARADDR The Low half-word of the DMA starting location in ARAM. The lower 5 bits are hard-wired to 0, effectively performing 32 byte alignment.


DSP_AR_DMA_SIZE_H (0xCC005028)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W R/W
Field Direction Size
Field Description
Direction The direction of DMA transfer. If 0, Write to ARAM. If 1, Read from ARAM.
Size The High half-word of the size of the DMA.

DSP_AR_DMA_SIZE_L (0xCC00502A)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W
Field Size
Field Description
Size The Low half-word of the size of the DMA. The lower 5 bits are hard-wired to 0, effectively performing 32 byte alignment.


ARAM Operations

Audio RAM (also called Auxillary RAM) is 16MB of (SDR?) SDRAM found only on the Gamecube. This SDRAM explanation from Wikipedia is very helpful.

Accesses are processed in a specific order by the ARAM controller. There are 3 accessors to ARAM: (the ARAM controller grants access to ARAM in the same order they are listed) ARAM Refresh, DSP Accelerators, and ARAM DMA. Note that as the bus is 64bits wide, and ARAM DMA has the lowest priority, it may be interrupted on 64bit boundaries if ARAM Refresh or DSP Accelerators are requesting access.

ARAM Refresh

ARAM Refresh is the interval at which ARAM banks will be refreshed by the ARAM controller. This takes time and thus must be scheduled along with other accesses.

DSP Accelerators

(TODO)

ARAM DMA

ARAM DMA is setup by writing to the various DSP_AR_DMA_* registers, and initiated by writing to DSP_AR_DMA_SIZE_L. The ARAM DMA is processed in 32byte units by loading data into a 32byte buffer and requesting ARAM access. After each 32byte unit is transferred, 32 is subtracted from the DSP_AR_DMA_SIZE register, and added to both the DSP_AR_DMA_MMADDR and DSP_AR_DMA_ARADDR registers.

It is impossible to DMA to/from unaligned addresses on the Gamecube, as the registers hardwire the low 5 bits to 0. However, on the Wii this causes a DSI exception (only tested in Wii mode, see below).

ARAM in Wii mode

ARAM does not physically exist in Wii hardware. However, the existence of ARAM seems to be faked to some extent (in Wii mode - haven't tested "GC mode"). For example, one can write to ARAM DMA registers and the DMA will seem to complete, however trying to read back data will always result in 0s.

It is interesting that writing an unaligned address as either MMADDR or ARADDR will cause DSI to be raised, even though nothing appears to be actually accessing any memory.

Audio Interface

This is the DMA from memory to the audio encoder. It can be seen as a circular buffer, although it can also behave as a "one-shot" buffer.

DSP_DMA_START_ADDR_H (0xCC005030)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access  ?/W
Field ADDR
Field Description
ADDR Not exactly sure what this is for. Top halfword of the address.

DSP_DMA_START_ADDR_L (0xCC005032)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access  ?/W
Field ADDR
Field Description
ADDR Not exactly sure what this is for. Bottom halfword of the address.


DSP_DMA_CONTROL_LENGTH (0xCC005036)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access  ?/W  ?/W
Field CTRL LENGTH
Field Description
CTRL If set, start playing the sample. If cleared, stop playing.
LENGTH Length of the sample divided by 32. The maximum value for this is 0x000FFFE0.

DSP_DMA_BYTES_LEFT (0xCC00503A)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/?
Field BYTES
Field Description
BYTES Count down to 0, counting how many bytes are left.
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