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Difference between revisions of "Hardware/DSP"

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(Initial stuff. Further adds to this page will be Minor Edits, to prevent spamming the Recent Changes.)
m (Less known registers.)
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|PIINT|DSP Interrupt Assertion? Setting asserts the DSP Interrupt.
 
|PIINT|DSP Interrupt Assertion? Setting asserts the DSP Interrupt.
 
|RES|Writing 1 resets the DSP.
 
|RES|Writing 1 resets the DSP.
 +
}}
 +
 +
{{reg16 | DSP_AR_SIZE | addr = 0xCC005012 | fields = 1 |
 +
|16  |
 +
|?  |
 +
|Size|
 +
|}}
 +
{{regdesc
 +
|Size|I can only guess that it's the size of the ARAM.
 +
}}
 +
 +
{{reg16 | DSP_AR_MODE | addr = 0xCC005016 | fields = 1 |
 +
|16  |
 +
|?  |
 +
|Mode|
 +
|}}
 +
{{regdesc
 +
|Mode|Some ARAM mode setting. Needs investigation.
 +
}}
 +
 +
{{reg16 | DSP_AR_REFRESH | addr = 0xCC00501A | fields = 1 |
 +
|16    |
 +
|?      |
 +
|Refresh|
 +
|}}
 +
{{regdesc
 +
|Refresh|Refreshes the ARAM?
 +
}}
 +
 +
{{reg16 | DSP_AR_DMA_SRC_H | addr = 0xCC005020 | fields = 1 |
 +
|16    |
 +
|?/W    |
 +
|SRCADDR|
 +
|}}
 +
{{regdesc
 +
|SRCADDR|The High half-word of the DMA Source.
 +
}}
 +
{{reg16 | DSP_AR_DMA_SRC_L | addr = 0xCC005022 | fields = 1 |
 +
|16    |
 +
|?/W    |
 +
|SRCADDR|
 +
|}}
 +
{{regdesc
 +
|SRCADDR|The Low half-word of the DMA Source.
 +
}}
 +
{{reg16 | DSP_AR_DMA_DST_H | addr = 0xCC005024 | fields = 1 |
 +
|16    |
 +
|?/W    |
 +
|DSTADDR|
 +
|}}
 +
{{regdesc
 +
|DSTADDR|The High half-word of the DMA Destination in ARAM.
 +
}}
 +
{{reg16 | DSP_AR_DMA_SRC_L | addr = 0xCC005026 | fields = 1 |
 +
|16    |
 +
|?/W    |
 +
|DSTADDR|
 +
|}}
 +
{{regdesc
 +
|DSTADDR|The Low half-word of the DMA Destination in ARAM.
 
}}
 
}}

Revision as of 23:31, 19 July 2009

DSP
Access
BroadwayFull
StarletNone
Registers
Base0x0c005000
Length0x200
Access size16/32 bits
Byte orderBig Endian
IRQs
Broadway6
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This Hardware-related article is a stub. You can help WiiBrew by expanding it.
This article may be improved with information from Yet Another GameCube Documentation. You can help WiiBrew by expanding this article with the information and wikifying it.

Excuse the crudity of these notes, they're written at 5:00 without any caffeine, and mostly copied from YAGCD with some nice formatting glue.

As the Infobox states, the base of this is at physical address 0x0C005000 (software address 0xCC005000)

Registers

DSP_MAILBOX_IN_H (0xCC005000)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W R/W
Field Set Data
Field Description
Set This must be set for the DSP to accept the data.
Data This, combined with the Data in DSP_MAILBOX_IN_L is the data being sent to the DSP.

DSP_MAILBOX_IN_L (0xCC005002)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W
Field Data
Field Description
Data This, combined with the Data in DSP_MAILBOX_IN_H is the data being sent to the DSP.


DSP_MAILBOX_OUT_H (0xCC005004)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R R
Field Set Data
Field Description
Set This must be set for the data to be valid.
Data This, combined with the Data in DSP_MAILBOX_OUT_L is the data being sent from the DSP.

DSP_MAILBOX_OUT_L (0xCC005006)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R
Field Data
Field Description
Data This, combined with the Data in DSP_MAILBOX_OUT_H is the data being sent from the DSP.


DSP_CONTROL_STATUS (0xCC00500A)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access U W W W W R/W W R/W W R/W R/W R/W R/W
Field Reset ? DMAINT DMAINTMSK DSPINT ARINTMSK ARINT AIDINTMSK AIDINT HALT PIINT RES
Field Description
Reset Resets the DSP?
DMAINT DSP DMA Interrupt Status
DMAINTMSK DSP Interrupt Mask
DSPINT DSP Interrupt Status. When read, set means Interrupt is active. Clear is no interrupts. Writing 0 does nothing, while writing 1 clears interrupt.
ARINTMSK ARAM Interrupt Mask
ARINT ARAM Interrupt Status. When read, set means Interrupt is active. Clear is no interrupts. Writing 0 does nothing, while writing 1 clears interrupt.
AIDINTMSK AI Interrupt Mask
AIDINT AI Interrupt Status. When read, set means Interrupt is active. Clear is no interrupts. Writing 0 does nothing, while writing 1 clears interrupt.
HALT Halt DSP? When set, the DSP will halt. When cleared, the DSP will resume.
PIINT DSP Interrupt Assertion? Setting asserts the DSP Interrupt.
RES Writing 1 resets the DSP.


DSP_AR_SIZE (0xCC005012)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ?
Field Size
Field Description
Size I can only guess that it's the size of the ARAM.


DSP_AR_MODE (0xCC005016)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ?
Field Mode
Field Description
Mode Some ARAM mode setting. Needs investigation.


DSP_AR_REFRESH (0xCC00501A)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ?
Field Refresh
Field Description
Refresh Refreshes the ARAM?


DSP_AR_DMA_SRC_H (0xCC005020)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ?/W
Field SRCADDR
Field Description
SRCADDR The High half-word of the DMA Source.

DSP_AR_DMA_SRC_L (0xCC005022)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ?/W
Field SRCADDR
Field Description
SRCADDR The Low half-word of the DMA Source.

DSP_AR_DMA_DST_H (0xCC005024)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ?/W
Field DSTADDR
Field Description
DSTADDR The High half-word of the DMA Destination in ARAM.

DSP_AR_DMA_SRC_L (0xCC005026)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ?/W
Field DSTADDR
Field Description
DSTADDR The Low half-word of the DMA Destination in ARAM.
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