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Difference between revisions of "Hardware/DSP"

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(New page: {{Infobox MMIO | ppc = Full | base = 0x0c005000 | len = 0x200 | bits = 16/32 | ppcirq = 6 }} {{hwstub}} {{yagcd}})
 
(Initial stuff. Further adds to this page will be Minor Edits, to prevent spamming the Recent Changes.)
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{{hwstub}}
 
{{hwstub}}
 
{{yagcd}}
 
{{yagcd}}
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Excuse the crudity of these notes, they're written at 5:00 without any caffeine, and mostly copied from YAGCD with some nice formatting glue.
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As the Infobox states, the base of this is at physical address 0x0C005000 (software address 0xCC005000)
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 +
== Registers ==
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{{reg16 | DSP_MAILBOX_IN_H | addr = 0xCC005000 | fields = 2 |
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|1  |15  |
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|R/W |R/W |
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|Set |Data|
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|}}
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{{regdesc
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|Set |This must be set for the DSP to accept the data.
 +
|Data|This, combined with the Data in DSP_MAILBOX_IN_L is the data being sent to the DSP.
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}}
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{{reg16 | DSP_MAILBOX_IN_L | addr = 0xCC005002 | fields = 1 |
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|16  |
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|R/W |
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|Data|
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|}}
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{{regdesc
 +
|Data|This, combined with the Data in DSP_MAILBOX_IN_H is the data being sent to the DSP.
 +
}}
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 +
{{reg16 | DSP_MAILBOX_OUT_H | addr = 0xCC005004 | fields = 2 |
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|1  |15  |
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|R  |R  |
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|Set |Data|
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|}}
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{{regdesc
 +
|Set |This must be set for the data to be valid.
 +
|Data|This, combined with the Data in DSP_MAILBOX_OUT_L is the data being sent from the DSP.
 +
}}
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{{reg16 | DSP_MAILBOX_OUT_L | addr = 0xCC005006 | fields = 1 |
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|16  |
 +
|R  |
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|Data|
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|}}
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{{regdesc
 +
|Data|This, combined with the Data in DSP_MAILBOX_OUT_H is the data being sent from the DSP.
 +
}}
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{{reg16 | DSP_CONTROL_STATUS | addr = 0xCC00500A | fields = 13 |
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|4 |1    |1 |1      |1        |1      |1        |1    |1        |1      |1    |1    |1  |
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|U |W    |W |W      |W        |R/W    |W        |R/W  |W        |R/W    |R/W  |R/W  |R/W |
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|  |Reset|? |DMAINT |DMAINTMSK |DSPINT |ARINTMSK |ARINT |AIDINTMSK |AIDINT |HALT |PIINT |RES |
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|}}
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{{regdesc
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|Reset|Resets the DSP?
 +
|DMAINT|DSP DMA Interrupt Status
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|DMAINTMSK|DSP Interrupt Mask
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|DSPINT|DSP Interrupt Status. When read, set means Interrupt is active. Clear is no interrupts. Writing 0 does nothing, while writing 1 clears interrupt.
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|ARINTMSK|ARAM Interrupt Mask
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|ARINT|ARAM Interrupt Status. When read, set means Interrupt is active. Clear is no interrupts. Writing 0 does nothing, while writing 1 clears interrupt.
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|AIDINTMSK|AI Interrupt Mask
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|AIDINT|AI Interrupt Status. When read, set means Interrupt is active. Clear is no interrupts. Writing 0 does nothing, while writing 1 clears interrupt.
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|HALT|Halt DSP? When set, the DSP will halt. When cleared, the DSP will resume.
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|PIINT|DSP Interrupt Assertion? Setting asserts the DSP Interrupt.
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|RES|Writing 1 resets the DSP.
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}}

Revision as of 23:15, 19 July 2009

DSP
Access
BroadwayFull
StarletNone
Registers
Base0x0c005000
Length0x200
Access size16/32 bits
Byte orderBig Endian
IRQs
Broadway6
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Excuse the crudity of these notes, they're written at 5:00 without any caffeine, and mostly copied from YAGCD with some nice formatting glue.

As the Infobox states, the base of this is at physical address 0x0C005000 (software address 0xCC005000)

Registers

DSP_MAILBOX_IN_H (0xCC005000)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W R/W
Field Set Data
Field Description
Set This must be set for the DSP to accept the data.
Data This, combined with the Data in DSP_MAILBOX_IN_L is the data being sent to the DSP.

DSP_MAILBOX_IN_L (0xCC005002)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W
Field Data
Field Description
Data This, combined with the Data in DSP_MAILBOX_IN_H is the data being sent to the DSP.


DSP_MAILBOX_OUT_H (0xCC005004)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R R
Field Set Data
Field Description
Set This must be set for the data to be valid.
Data This, combined with the Data in DSP_MAILBOX_OUT_L is the data being sent from the DSP.

DSP_MAILBOX_OUT_L (0xCC005006)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R
Field Data
Field Description
Data This, combined with the Data in DSP_MAILBOX_OUT_H is the data being sent from the DSP.


DSP_CONTROL_STATUS (0xCC00500A)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access U W W W W R/W W R/W W R/W R/W R/W R/W
Field Reset ? DMAINT DMAINTMSK DSPINT ARINTMSK ARINT AIDINTMSK AIDINT HALT PIINT RES
Field Description
Reset Resets the DSP?
DMAINT DSP DMA Interrupt Status
DMAINTMSK DSP Interrupt Mask
DSPINT DSP Interrupt Status. When read, set means Interrupt is active. Clear is no interrupts. Writing 0 does nothing, while writing 1 clears interrupt.
ARINTMSK ARAM Interrupt Mask
ARINT ARAM Interrupt Status. When read, set means Interrupt is active. Clear is no interrupts. Writing 0 does nothing, while writing 1 clears interrupt.
AIDINTMSK AI Interrupt Mask
AIDINT AI Interrupt Status. When read, set means Interrupt is active. Clear is no interrupts. Writing 0 does nothing, while writing 1 clears interrupt.
HALT Halt DSP? When set, the DSP will halt. When cleared, the DSP will resume.
PIINT DSP Interrupt Assertion? Setting asserts the DSP Interrupt.
RES Writing 1 resets the DSP.
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