Hollywood/GPIOs

GPIOs
Hollywood Registers
Access
Broadway	Partial
Starlet	Full
Registers
Base	0x0d8000c0
Length	0x40
Access size	32 bits
Byte order	Big Endian
IRQs
Hollywood	10, 11

The Hollywood chipset includes 24 general purpose I/O lines with interrupt capability. Two full sets of registers are provided, and the Broadway only has access to one half. Each pin can be assigned to one of the two sets of registers, which lets the Starlet control which pins only it can control, and which pins the Broadway can use too.

Pin connections

Bit	Direction	Connection	Description
0	IN	POWER	Power button input (pulse width limited; will not detect a held-down state).
1	OUT	SHUTDOWN	Output high to turn system off (Power LED = red).
2	OUT	FAN	Fan power, active high.
3	OUT	DC_DC	DC/DC converter power, active high (powers the Broadway?[check]). When off, also triggers the Yellow power LED.
4	OUT	DI_SPIN	DI Spinup enable? Not sure[check].
5	OUT	SLOT_LED	Blue disc slot LED, active high.
6	IN	EJECT_BTN	Eject button (pulse width limited). Button press will also trigger the drive directly.
7	IN	SLOT_IN	Disc slot optical detector. High if disc in drive, disc being inserted, or disc still in slot after eject.
8	OUT	SENSOR_BAR	Sensor bar, active high.
9	OUT	DO_EJECT	Pulse high to trigger a DI eject from software.
10	OUT	EEP_CS	SEEPROM Chip Select.
11	OUT	EEP_CLK	SEEPROM Clock.
12	OUT	EEP_MOSI	Data to SEEPROM.
13	IN	EEP_MISO	Data from SEEPROM.
14	OUT	AVE_SCL	A/V Encoder I²C Clock.
15	I/O	AVE_SDA	A/V Encoder I²C Data (has an external pull-up, so you should only drive it low).
16	OUT	DEBUG0	Debug Testpoint TP221.
17	OUT	DEBUG1	Debug Testpoint TP222.
18	OUT	DEBUG2	Debug Testpoint TP223.
19	OUT	DEBUG3	Debug Testpoint TP224.
20	OUT	DEBUG4	Debug Testpoint TP225.
21	OUT	DEBUG5	Debug Testpoint TP226.
22	OUT	DEBUG6	Debug Testpoint TP219.
23	OUT	DEBUG7	Debug Testpoint TP220.

Register list

Hollywood GPIOs
Address	Bits	Name	Description
0x0d8000c0	32	HW_GPIOB_OUT	GPIO Outputs (Broadway access)
0x0d8000c4	32	HW_GPIOB_DIR	GPIO Direction (Broadway access)
0x0d8000c8	32	HW_GPIOB_IN	GPIO Inputs (Broadway access)
0x0d8000cc	32	HW_GPIOB_INTLVL	GPIO Interrupt Levels (Broadway access)
0x0d8000d0	32	HW_GPIOB_INTFLAG	GPIO Interrupt Flags (Broadway access)
0x0d8000d4	32	HW_GPIOB_INTMASK	GPIO Interrupt Masks (Broadway access)
0x0d8000d8	32	HW_GPIOB_INMIR	GPIO Input Mirror (Broadway access)
0x0d8000dc	32	HW_GPIO_ENABLE	GPIO Enable (Starlet only)
0x0d8000e0	32	HW_GPIO_OUT	GPIO Outputs (Starlet only)
0x0d8000e4	32	HW_GPIO_DIR	GPIO Direction (Starlet only)
0x0d8000e8	32	HW_GPIO_IN	GPIO Inputs (Starlet only)
0x0d8000ec	32	HW_GPIO_INTLVL	GPIO Interrupt Levels (Starlet only)
0x0d8000f0	32	HW_GPIO_INTFLAG	GPIO Interrupt Flags (Starlet only)
0x0d8000f4	32	HW_GPIO_INTMASK	GPIO Interrupt Masks (Starlet only)
0x0d8000f8	32	HW_GPIO_INMIR	GPIO Input Mirror (Starlet only)
0x0d8000fc	32	HW_GPIO_OWNER	GPIO Owner Select (Starlet only)

Register descriptions

HW_GPIO_ENABLE (0x0d8000dc)
	3124	230
Access	U	R/W

The bits of this register indicate whether specific GPIO pins are enabled. The typical value is 0xFFFFFF, to enable all pins.

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HW_GPIO_OUT (0x0d8000e0)
	3124	230
Access	U	R/W

This register contains the output value for all pins. These only take effect if the pin is configured as an output.

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HW_GPIO_DIR (0x0d8000e0)
	3124	230
Access	U	R/W

A '1' bit for a pin indicates that it will behave as an output (drive), while a '0' bit tristates the pin and it becomes a high-impedance input.

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HW_GPIO_IN (0x0d8000e0)
	3124	230
Access	U	R

This register can be read to obtain the current input value of the GPIO pins.

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HW_GPIO_INTLVL (0x0d8000e0)
	3124	230
Access	U	R/W

Configures the pin state that causes an interrupt. If a bit is set in this register, the pin causes an interrupt when high (or on the rising edge?^[check]). A zero causes the opposite behavior.

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HW_GPIO_INTFLAG (0x0d8000f0)
	3124	230
Access	U	R/Z

Bits in this register indicate which pins have triggered their interrupt flags. Write one to clear a bit back to zero.

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HW_GPIO_INTMASK (0x0d8000f4)
	3124	230
Access	U	R/W

Only the bits set in this register propagate their interrupts to the master Starlet GPIO interrupt (#11). All other pin interrupts are ignored, although the interrupt state can still be queried and cleared in HW_GPIO_INTFLAG.

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HW_GPIO_INMIR (0x0d8000f8)
	3124	230
Access	U	R/W

This register appears to contain the input state at some point in time, possibly power-on or interrupt or something like that. ^[check]

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HW_GPIO_OWNER (0x0d8000fc)
	3124	230
Access	U	R/W

This register configures which pins are controlled with HW_GPIO registers vs HW_GPIOB registers. A one bit configures the pin for control via the HW_GPIOB registers, and enables access by the Broadway. A zero bit restricts access to the HW_GPIO registers, which are Starlet-only.

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HW_GPIOB_OUT (0x0d8000c0)
	3124	230
Access	U	R/W

HW_GPIOB_DIR (0x0d8000c4)
	3124	230
Access	U	R/W

HW_GPIOB_IN (0x0d8000c8)
	3124	230
Access	U	R

HW_GPIOB_INTLVL (0x0d8000cc)
	3124	230
Access	U	R/W

HW_GPIOB_INTFLAG (0x0d8000d0)
	3124	230
Access	U	R/Z

HW_GPIOB_INTMASK (0x0d8000d4)
	3124	230
Access	U	R/W

HW_GPIOB_INMIR (0x0d8000d8)
	3124	230
Access	U	R/W

These registers operate identically to their HW_GPIO counterparts above, but they control the pins which have their respective HW_GPIO_OWNER bits set to 1. They can be accessed by the Broadway, although their interrupt (HW_GPIOB_INTFLAG & HW_GPIOB_INTMASK) is mapped to Starlet IRQ #10.