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4,022 bytes added ,  14:13, 16 September 2015
m
Capitalization, regs -> registers
This is a warning to the owners of this site. My name is Shigeru Miyamoto and I am disappoint. You are breaking the DCMA laws. DCMA laws protect our freedoms far into the furture. There is over 9000 pages here and I want every single one of them gone by next week. This is not a threat but a promise. Every day after that week is up, I will sue you for $100,000 a day.{| class="wikitable"|-! Start Address! End Address! Physical Address! Size! Description|-| 0x00000000| 0x017FFFFF| 0x00000000| 24 MB| MEM1 Memory|-| 0x10000000| 0x13FFFFFF| 0x10000000| 64 MB| MEM2 Memory|-| 0x0D000000| | 0x0D000000| | Hardware Registers|-| 0x0D400000| | 0x0D400000| | Internal SRAM|-| 0x0D800000| | 0x0D800000| | Hardware Registers|-| 0xFFF00000| 0xFFFFFFFF| | | Internal SRAM (mirror)|}
Thank you for using NintendoHollywood I/O registers are at 0x0D80xxxx (Starlet private) and 0x0D00xxxx (shared with the Broadway). We must ensure our freedoms through use That is to say, the contents of the DCMA0x0D80xxxx are selectively mirrored to 0x0D0xxxxx. The Broadway "sees" 0x0D00xxxx when it tries to access 0x0D80xxxx (that address bit is forced to zero). This not changes depending on some of the analog millennium one passed in 1000 Aregisters (e.g.Dwhen MIOS is active).Starlet private peripherals, however, but live in 0x0D0yxxxx for y!=0 and the digital oneBroadway can't see them.
==CEASE==The GDDR3 is at 0x10000000, 64MB of it; a configurable range is exclusive for use by the Starlet (IOS reserves the top 12MB), the rest is shared with the Broadway.AND DESIST0x0D0xxxxx may be an [http://www.arm.com/products/solutions/amba2overview.html AMBA AHB] bus. The Starlet internal SRAM (96kB) mappings are weird (someone wikify this): <pre><nowiki>SRAM and BOOT0 map into two main canonical areas (with tons of mirrors): - 0x0d400000 - 0x0d41ffff - 0xfffe0000 - 0xffffffff Mirrors of note: 0xfff00000-0xfff1ffff is equivalent to 0x0d400000-0x0d41ffff.This is actually mirrored until 0xfffe0000 (or 0xffff0000 if you count half a mirroring block), where the mapping starts to differ. BOOT0 runs from 0xffff0000 and loads BOOT1 into 0x0d400000, with HOLLYWOOD[0x60]&0x20 offBOOT1 runs from 0xfff00000 and 0x0d400000, with HOLLYWOOD[0x60]&0x20 off(BOOT1 seems to be compiled at 0x0d400000 but is called at 0xfff00000, so the program flow continuously switches between them as it goes through jump tables or back out through the stack and relative jumps)BOOT2LOADER runs from MEM1, switches HOLLYWOOD[0x60]&0x20 on, then loads BOOT2BOOT2/IOS runs from 0xffff0000, switches off BOOT0, then uses 0xfffe0000 as data RAM too, with HOLLYWOOD[0x60]&0x20 on These are the maps: --- BOOT0 enabled ---  HOLLYWOOD[0x60]&0x20 clear HOLLYWOOD[0x60]&0x20 set  fff00000 fff00000 0d400000 fffe0000 0d400000 fffe0000+---------+ +---------+ +---------+ +---------+ +00000| | | | | | | || | | | | | | || | | | | | | || SRAM A | | SRAM A | | | | BOOT0 | +08000| | | | | | | x8 || | | | | | | || | | | | | | |+---------+ +---------+ | BOOT0 | +---------+ +10000| | | | | x16 | | || SRAM B | | | | | | || | | | | | | |+---------+ | BOOT0 | | | | SRAM A | +18000| | | x8 | | | | || JUNK | | | | | | || | | | | | | |+---------+ +---------+ +---------+ +---------+ +20000 --- BOOT0 disabled ---  HOLLYWOOD[0x60]&0x20 clear HOLLYWOOD[0x60]&0x20 set  fff00000 fff00000 0d400000 fffe0000 0d400000 fffe0000+---------+ +---------+ +---------+ +---------+ +00000| | | | | | | || | | | | SRAM B | | SRAM B || | | | | | | || SRAM A | | SRAM A | +---------+ +---------+ +08000| | | | | | | || | | | | JUNK | | JUNK || | | | | | | |+---------+ +---------+ +---------+ +---------+ +10000| | | | | | | || SRAM B | | SRAM B | | | | || | | | | | | |+---------+ +---------+ | SRAM A | | SRAM A | +18000| | | | | | | || JUNK | | JUNK | | | | || | | | | | | |+---------+ +---------+ +---------+ +---------+ +20000 </nowiki></pre> [[Category:Hardware]]
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