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Hardware/GX/Command Processor (view source)
Revision as of 01:03, 12 July 2010
, 01:03, 12 July 2010Added clear and token
Line 36:
Line 36:
|FIFOE|FIFO read enable (disable while setting up) (default 1)
|FIFOE|FIFO read enable (disable while setting up) (default 1)
}}
}}
+{{reg16 | CP_CLEAR | addr = 0xCC000004 | fields = 3 |
+|14|1 |1 |
+|U |R/W |R/W |
+| |Under|Over |
+|}}
+{{regdesc
+|Under|Write 1 to clear FIFO underflow
+|Over|Write 1 to clear FIFO overflow
+}}
+{{regsimple | CP_TOKEN | addr=0xCC00000E | bits=16 | access = R}}
+This register contains the last token that was read from the FIFO.
{{regsimple | CP_FIFO_START | addr=0xCC000020 | bits=32 | access = R/W}}
{{regsimple | CP_FIFO_START | addr=0xCC000020 | bits=32 | access = R/W}}
WARNING: This CP register is actually two 16 bit registers. Though it is big endian, a bug in the hardware means the two 16 bit halves will be swapped if you write to it 32-bit. You have been warned!
WARNING: This CP register is actually two 16 bit registers. Though it is big endian, a bug in the hardware means the two 16 bit halves will be swapped if you write to it 32-bit. You have been warned!