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The PowerPC is a RISC (Reduced Instruction Set Computing) processor architecture. PowerPC is an acronym which shall stand for Performance Optimization With Enhanced RISC / Performance Chip or Power Performance Computing. The specification for it was released in 1993 and is a 64-bit specification with a 32-bit subset. Almost all PowerPC processors are 32-bit now but feature a 64-bit data bus.

The PowerPC is a RISC (Reduced Instruction Set Computing) processor architecture. PowerPC is an acronym which shall stand for Performance Optimization With Enhanced RISC / Performance Chip or Power Performance Computing. The specification for it was released in 1993 and is a 64-bit specification with a 32-bit subset. Almost all PowerPC processors are 32-bit now but feature a 64-bit data bus.

The PowerPC was developed jointly by Apple, IBM and Motorola (now named Freescale). There are many different PowerPC processors available. Apple has been using the PowerPC in the Macintosh systems, IBM is using it in its RS/6000 and pSeries computers und Nintendo used it in its Gamecube and in Wii playstations. There are many embedded applications using the PowerPC.

The PowerPC was developed jointly by Apple, IBM and Motorola (now named Freescale). There are many different PowerPC processors available. Apple has been using the PowerPC in the Macintosh systems, IBM is using it in its RS/6000 and pSeries computers und Nintendo used it in its Gamecube and in Wii playstations. There are many embedded applications using the PowerPC.

==The registers==

== The registers ==

The PowerPC has many more registers than the Intel processors and these are named differently. All registers are 4 bytes or 32bits long on the 32-bit versions of the PowerPC. There are 32 (0-31) General Purpose Registers (GPRs or rX), 32 Floating point registers (FPRs or fX) and special purpose registers (SPRs) like the program counter PC or IAR (instruction address register). This keeps track which instruction needs to be executed next. There is a link register (LR) which can hold the address of a procedure for branch instructions, the condition register (CR) which has eight (0-7) 4 bit fields holding the result of e.g. a compare instruction. The count register for loops is called CTR. XER is the fixed-point exception register. FPSCR is the floating point status and control register.

The PowerPC has many more registers than the Intel processors and these are named differently. All registers are 4 bytes or 32bits long on the 32-bit versions of the PowerPC. There are 32 (0-31) General Purpose Registers (GPRs or rX), 32 Floating point registers (FPRs or fX) and special purpose registers (SPRs) like the program counter PC or IAR (instruction address register). This keeps track which instruction needs to be executed next. There is a link register (LR) which can hold the address of a procedure for branch instructions, the condition register (CR) which has eight (0-7) 4 bit fields holding the result of e.g. a compare instruction. The count register for loops is called CTR. XER is the fixed-point exception register. FPSCR is the floating point status and control register.

==Variables==

== Variables ==

The 32-bit version of the PowerPC supports the following data sizes:

The 32-bit version of the PowerPC supports the following data sizes:

<tt>

<tt>

:Byte       - 8 bits

:Byte - 8 bits

:Halfword   - 16 bits

:Halfword - 16 bits

:Word       - 32 bits

:Word - 32 bits

</tt>

</tt>

Here are examples how to define variables. The name of the variable is always set as a label followed by a colon.

Here are examples how to define variables. The name of the variable is always set as a label followed by a colon.

<tt>

<tt>

:bytevar: .byte 0   #length of one byte - init zero

:bytevar: .byte 0 #length of one byte - init zero

:shortvar: .short 0 #length of two byte - init zero

:shortvar: .short 0 #length of two byte - init zero

:wordvar: .long 0   #length of four byte - init zero

:wordvar: .long 0 #length of four byte - init zero

<br>

<br />

:fivebytevar: .byte 11,12,13,14,15 #an array of five variables of one byte each

:fivebytevar: .byte 11,12,13,14,15 #an array of five variables of one byte each

:endof_fivebytevar: #specifies the address immediately following the array

:endof_fivebytevar: #specifies the address immediately following the array

<br>

<br />

:stringvar: .string "Hello\n" #string variable - init to "Hello" plus newline

:stringvar: .string "Hello\n" #string variable - init to "Hello" plus newline

::           .size stringvarlen, .-stringvar #length of stringvar

:: .size stringvarlen, .-stringvar #length of stringvar

</tt>

</tt>

==Constants==

== Constants ==

The AS assembler allows to define constants. These will be replaced by the assembler before assembling the code.

The AS assembler allows to define constants. These will be replaced by the assembler before assembling the code.

==Instructions and Mnemonics==

== Instructions and Mnemonics ==

Assembler instructions for Intel processors have up to two parameters separated by a comma. Typically the first parameter is modified with the second.

Assembler instructions for Intel processors have up to two parameters separated by a comma. Typically the first parameter is modified with the second.

<tt>

<tt>

:Opcode:               6 bits

:Opcode: 6 bits

:Source register:       5 bits

:Source register: 5 bits

:Destination register: 5 bits

:Destination register: 5 bits

:Immediate value:     16 bits

:Immediate value: 16 bits

</tt>

</tt>

===Integer Instructions===

=== Integer Instructions ===

====Integer Arithmetic Instructions====

==== Integer Arithmetic Instructions ====

=====ADD=====

===== ADD =====

This instructions has several variants:

This instructions has several variants:

=====SUBF - Subtract From=====

===== SUBF - Subtract From =====

=====MUL - Multiply=====

===== MUL - Multiply =====

Multiplying two 32-bit values will often result in a 64-bit value. So there are separate instructions to put the 64-bit result into two 32-bit registers:

Multiplying two 32-bit values will often result in a 64-bit value. So there are separate instructions to put the 64-bit result into two 32-bit registers:

=====DIV - Divide=====

===== DIV - Divide =====

'''divw - Divide Word'''

'''divw - Divide Word'''

====Integer Compare und Logical Instructions====

==== Integer Compare und Logical Instructions ====

1. '''CMP - Compare'''

1. '''CMP - Compare'''

=====OR=====

===== OR =====

1. '''OR'''

1. '''OR'''

=====AND=====

===== AND =====

1. '''AND'''

1. '''AND'''

====Integer shift and rotate instructions====

==== Integer shift and rotate instructions ====

1. '''SLW - Shift left word'''

1. '''SLW - Shift left word'''

===Floating point instructions===

=== Floating point instructions ===

===Load and Store Instructions===

=== Load and Store Instructions ===

The PowerPC allows just to move data from register to memory and from memory to register. You cannot copy directly from one memory location to another.

The PowerPC allows just to move data from register to memory and from memory to register. You cannot copy directly from one memory location to another.

===Branch instructions===

=== Branch instructions ===

The PowerPC branch instructions are similar to the Intel Processor's jmp and call commands.

The PowerPC branch instructions are similar to the Intel Processor's jmp and call commands.

<tt>

<tt>

:beq - branch if equal     | example: beq 7,testlabel

:beq - branch if equal | example: beq 7,testlabel

:bne - branch if not equal | example: bne 7,testlabel

:bne - branch if not equal | example: bne 7,testlabel

:blt - branch if less than | example: blt 7,testlabel

:blt - branch if less than | example: blt 7,testlabel

===Various instructions===

=== Various instructions ===

==Application Binary Interface (SVR4 ABI)==

== Application Binary Interface (SVR4 ABI) ==

On Intel processors external subroutines and functions are usually called by pushing the arguments to be passed to the subroutine on the stack. The subroutine then sets up a stack frame and reads the parameters from the stack.

On Intel processors external subroutines and functions are usually called by pushing the arguments to be passed to the subroutine on the stack. The subroutine then sets up a stack frame and reads the parameters from the stack.