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Line 96:
Line 96: − + − + − +
Corrected error in individual GPIO reg addresses.
This register contains the output value for all pins. These only take effect if the pin is configured as an output.
This register contains the output value for all pins. These only take effect if the pin is configured as an output.
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{{regsimple2|HW_GPIO_DIR|addr=0x0d8000e0|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIO_DIR|addr=0x0d8000e4|bits=32|split=24|access=R/W}}
A '1' bit for a pin indicates that it will behave as an output (drive), while a '0' bit tristates the pin and it becomes a high-impedance input.
A '1' bit for a pin indicates that it will behave as an output (drive), while a '0' bit tristates the pin and it becomes a high-impedance input.
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{{regsimple2|HW_GPIO_IN|addr=0x0d8000e0|bits=32|split=24|access=R}}
{{regsimple2|HW_GPIO_IN|addr=0x0d8000e8|bits=32|split=24|access=R}}
This register can be read to obtain the current input value of the GPIO pins.
This register can be read to obtain the current input value of the GPIO pins.
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{{regsimple2|HW_GPIO_INTLVL|addr=0x0d8000e0|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIO_INTLVL|addr=0x0d8000ec|bits=32|split=24|access=R/W}}
Configures the pin state that causes an interrupt. If a bit is set in this register, the pin causes an interrupt when high. A zero causes the opposite behavior.
Configures the pin state that causes an interrupt. If a bit is set in this register, the pin causes an interrupt when high. A zero causes the opposite behavior.
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