Changes

|FIFOE|FIFO read enable (disable while setting up) (default 1)

|FIFOE|FIFO read enable (disable while setting up) (default 1)

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{{regsimple | GX_CP_FIFO_START_L | addr=0xCC000020 | bits=16 | access = R/W}}

{{regsimple | GX_CP_FIFO_START  | addr=0xCC000020 | bits=32 | access = R/W}}

{{regsimple | GX_CP_FIFO_START_H | addr=0xCC000022 | bits=16 | access = R/W}}

WARNING: This CP register is actually two 16 bit registers. Though it is big endian, a bug in the hardware means the two 16 byte halves will be swapped if you write to it 32-bit. You have been warned!

{{regsimple | GX_CP_FIFO_END_L  | addr=0xCC000024 | bits=16 | access = R/W}}

{{regsimple | GX_CP_FIFO_END    | addr=0xCC000024 | bits=32 | access = R/W}}

{{regsimple | GX_CP_FIFO_END_H  | addr=0xCC000026 | bits=16 | access = R/W}}

WARNING: This CP register is actually two 16 bit registers. Though it is big endian, a bug in the hardware means the two 16 byte halves will be swapped if you write to it 32-bit. You have been warned!

{{regsimple | GX_CP_FIFO_WP_L    | addr=0xCC000034 | bits=16 | access = R/W}}

{{regsimple | GX_CP_FIFO_WP      | addr=0xCC000034 | bits=32 | access = R/W}}

{{regsimple | GX_CP_FIFO_WP_H    | addr=0xCC000036 | bits=16 | access = R/W}}

WARNING: This CP register is actually two 16 bit registers. Though it is big endian, a bug in the hardware means the two 16 byte halves will be swapped if you write to it 32-bit. You have been warned!

{{regsimple | GX_PI_FIFO_WP      | addr=0xCC003014 | bits=32 | access = R/W}}

{{regsimple | GX_PI_FIFO_WP      | addr=0xCC003014 | bits=32 | access = R/W}}

===BP (blitting processor) registers===

===BP (blitting processor) registers===