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Line 33:
Line 33: + + + + + + + + + + + + +
→FIFO Setup: new register!
|UF|FIFO underflow (Determined by watermark registers?
|UF|FIFO underflow (Determined by watermark registers?
|OF|FIFO overflow ("")
|OF|FIFO overflow ("")
}}
{{reg16 | GX_CP_CONTROL | addr = 0xCC000001 | fields = 7 |
|10|1 |1 |1 |1 |1 |1 |
|U |R/W|R/W |R/W |R/W |R/W |R/W |
| |BPE|GPLE|UFInt|OFInt|CPInt|FIFOE|
|}}
{{regdesc
|BPE|Blitting processor enable
|GPLE|FIFO link enable (YAGCD says CP->PE?)
|UFInt|FIFO underflow interrupt
|OFInt|FIFO overflow interrupt
|CPInt|Command Processor interrupt
|FIFOE|FIFO read enable (disable while setting up)
}}
}}
===BP (blitting processor) registers===
===BP (blitting processor) registers===