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This register controls the state of the AES engine.
This register controls the state of the AES engine.
{{regdesc
{{regdesc
−|EXEC|Write 1: initiate AES command<br/>Read: AES engine busy
+|EXEC|Write 1: initiate AES command<br/>Write 0: reset AES engine<br/>Read: AES engine busy
|IRQ|Set to enable IRQ generation when command is complete
|IRQ|Set to enable IRQ generation when command is complete
|ERR|If set, AES error occured (?){{check}}
|ERR|If set, AES error occured (?){{check}}