Changes

This register implements a FIFO that accepts the AES key. A sequence of four 32-bit writes will set the AES key (starting with the leftmost 32-bit word).

This register implements a FIFO that accepts the AES key. A sequence of four 32-bit writes will set the AES key (starting with the leftmost 32-bit word).

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{{regsimple | AES_IV | addr = 0x0d02000c | bits = 32 | access = W }}

{{regsimple | AES_IV | addr = 0x0d020010 | bits = 32 | access = W }}

This register implements a FIFO that accepts the AES IV. A sequence of four 32-bit writes will set the AES IV (starting with the leftmost 32-bit word).

This register implements a FIFO that accepts the AES IV. A sequence of four 32-bit writes will set the AES IV (starting with the leftmost 32-bit word).

Clear the IV bit in the [[#AES_CTRL|AES_CTRL]] register to restart the CBC encryption using this IV instead of using the last encrypted block.

Clear the IV bit in the [[#AES_CTRL|AES_CTRL]] register to restart the CBC encryption using this IV instead of using the last encrypted block.