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Hardware/NAND Interface (view source)

Revision as of 18:43, 5 March 2009

1,843 bytes added ,  18:43, 5 March 2009
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Reverted edits by IMacros (Talk) to last version by Bushing
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これは日本のニンテンドーfucking ！私は神のCEOは、午前くそー！お客様の製品やfucking私fucking私のfuckingの雌ロバが改造停止を訴える！あなたファック
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{{Infobox MMIO
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| arm = Full
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=これは日本のニンテンドーfucking ！私は神のCEOは、午前くそー！お客様の製品やfucking私fucking私のfuckingの雌ロバが改造停止を訴える！あなたファック=
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| base = 0x0d010000
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==これは日本のニンテンドーfucking ！私は神のCEOは、午前くそー！お客様の製品やfucking私fucking私のfuckingの雌ロバが改造停止を訴える！あなたファック==
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| len = 0x1C
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===これは日本のニンテンドーfucking ！私は神のCEOは、午前くそー！お客様の製品やfucking私fucking私のfuckingの雌ロバが改造停止を訴える！あなたファック===
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| bits = 32
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これは日本のニンテンドーfucking ！私は神のCEOは、午前くそー！お客様の製品やfucking私fucking私のfuckingの雌ロバが改造停止を訴える！あなたファック
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| armirq = 1
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====これは日本のニンテンドーfucking ！私は神のCEOは、午前くそー！お客様の製品やfucking私fucking私のfuckingの雌ロバが改造停止を訴える！あなたファック=====
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}}
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== Register List ==
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これは日本のニンテンドーfucking ！私は神のCEOは、午前くそー！お客様の製品やfucking私fucking私のfuckingの雌ロバが改造停止を訴える！あなたファック
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{{reglist|NAND Interface}}
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{{rla|0x0d010000|32|NAND_CTRL|NAND Control and Status}}
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[[これは日本のニンテンドーfucking ！私は神のCEOは、午前くそー！お客様の製品やfucking私fucking私のfuckingの雌ロバが改造停止を訴える！あなたファック]]
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{{rla|0x0d010004|32|NAND_CONFIG|??}}
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{{rla|0x0d010008|32|NAND_ADDR1|Address bytes 1-2 (column)}}
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[これは日本のニンテンドーfucking ！私は神のCEOは、午前くそー！お客様の製品やfucking私fucking私のfuckingの雌ロバが改造停止を訴える！あなたファック]
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{{rla|0x0d01000c|32|NAND_ADDR2|Address bytes 3-5 (row)}}
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{{rla|0x0d010010|32|NAND_DATABUF|Memory address of the Data buffer}}
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{{rla|0x0d010014|32|NAND_ECCBUF|Memory address of the Spare buffer}}
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{{rla|0x0d010018|32|NAND_UNK|Unknown}}
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|}
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== Register Details ==
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{{reg32 | NAND_CTRL | addr = 0x0d010000 | hifields = 9 | lofields = 5 |
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|1|1|1|1|1|1|1|1|8|
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|R/W|W|U|W|W|W|W|W|W|
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|EXEC|IRQ||A5|A4|A3|A2|A1|COMMAND||
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|1|1|1|1|12|
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|W|W|W|W|W|
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|WAIT|WR|RD|ECC|DMALEN|
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}}
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This register controls the state of the NAND interface.
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{{regdesc
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|EXEC|Write 1: initiate NAND command<br/>Read: NAND interface busy
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|IRQ|Set to enable IRQ generation when command is complete
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|A5|Send fifth address byte (typ. row address high)
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|A4|Send fourth address byte (typ. row address mid)
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|A3|Send third address byte (typ. row address low)
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|A2|Send second address byte (typ. column address high)
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|A1|Send first address byte (typ. column address low)
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|COMMAND|8-bit NAND command
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|WAIT|Wait for R/B to go high between address and data phases (wait for read/write/erase){{check}}
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|WR|Transfer data to the NAND chip{{check}}
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|RD|Transfer data from the NAND chip{{check}}
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|ECC|Calculate ECC or transfer ECC data or ?? {{check}}
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|DMALEN|Number of bytes to transfer
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}}
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----
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{{reg32 | NAND_CONFIG | addr = 0x0d010004 | hifields = 4 | lofields = 2 |
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|4|1|4|8|
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|R/W|R/W|R/W|R/W|
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|ATTR0|ENABLE|ATTR1|ATTR2||
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|8|8|
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|R/W|R/W|
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|ATTR3|ATTR4|
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}}
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This register probably configures certain aspects of the NAND interface (timings?){{check}}.
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{{regdesc
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|ATTR0|Set based on lookup table; set to 3 for 128MB NAND chips, 4 otherwise
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|ENABLE|Set to 1 before first command is sent to NAND, set to 0 when de-initializing the NAND driver.
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|ATTR1|Set based on lookup table; always 0x3
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|ATTR2|Set based on lookup table; always 0x3e
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|ATTR3|Set based on lookup table; always 0x0e
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|ATTR4|Set based on lookup table; always 0x7f
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}}
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When IOS initializes the NAND driver, it turns on the enable bit (writing 0x08000000) and then send the GET CHIP ID command (0x90).  Based on the reply, it looks up the correct definitions of the other attributes and pokes them into this register (generally, 0x4b3e0e7f).
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----
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{{reg32 | NAND_ADDR1 | addr = 0x0d010008 | hifields = 1 | lofields = 2 |
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|16|
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|U|
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|||
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|8|8|
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|R/W|R/W|
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|ADDR2|ADDR1|
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}}
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This register contains the first two address bytes that can be sent to the NAND chip. Normally it contains the column address (offset within a page).
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{{regdesc
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|ADDR2|Second address byte
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|ADDR1|First address byte
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}}
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----
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{{reg32 | NAND_ADDR2 | addr = 0x0d01000c | hifields = 2 | lofields = 2 |
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|8|8|
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|U|R/W|
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||ADDR5||
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|8|8|
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|R/W|R/W|
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|ADDR4|ADDR3|
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}}
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This register contains the last three address bytes that can be sent to the NAND chip. Normally it contains the row address (page number).
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{{regdesc
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|ADDR5|Fifth address byte
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|ADDR4|Fourth address byte
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|ADDR3|Third address byte
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}}
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----
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{{regsimple | NAND_DATABUF | addr = 0x0d010010 | bits = 32 | access = R/W }}
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This register contains the DMA address of the page data buffer (0x800 bytes)
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----
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{{regsimple | NAND_ECCBUF | addr = 0x0d010014 | bits = 32 | access = R/W }}
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This register contains the DMA address of the spare and ECC data buffer (0x40 spare bytes + 0x10 bytes of hardware-calculated ECC syndrome).
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----
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{{regsimple | NAND_UNK | addr = 0x0d010018 | bits = 32 | access = R/W }}
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This register has an unknown function; boot2 writes 1 to it when reloading to a new IOS.
Retrieved from "https://wiibrew.org/wiki/Special:MobileDiff/45069"

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