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move memory map
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== Memory map ==
−{| class="wikitable"
−|-
−! Start Address
−! End Address
−! Physical Address
−! Size
−! Description
−|-
−| 0x00000000
−| 0x017FFFFF
−| 0x00000000
−| 24 MB
−| MEM1 Memory (Cached)
−|-
−| 0x10000000
−| 0x13FFFFFF
−| 0x10000000
−| 64 MB
−| MEM2 Memory (Cached)
−|-
−| 0x0D000000
−|
−| 0x0D000000
−|
−| Hardware Registers (shared with the Broadway)
−|-
−| 0x0D400000
−|
−| 0x0D400000
−|
−| RAM used for program code, data and stack
−|-
−| 0x0D800000
−|
−| 0x0D800000
−|
−| Hardware Registers (Starlet private)
−|-
−| 0xFFFE0000
−| 0xFFFFFFFF
−|
−|
−| Internal SRAM
−|}
−I/O is at 0x0D800000 (Starlet private) and 0x0D000000 (shared with the Broadway). That is to say, the contents of 0x0D8xxxxx are selectively mirrored to 0x0D0xxxxx. This may change depending on some of the registers (e.g. when MIOS is active).
−There is internal SRAM at 0xFFFE0000, 128kB of it; this stores the kernel code and data, minus the crypto code.
−The GDDR3 is at 0x10000000, 64MB of it; the upper 12MB are exclusive for use by the Starlet, the rest is shared with the Broadway.
−0x0D0xxxxx may be an [http://www.arm.com/products/solutions/amba2overview.html AMBA AHB] bus.
This page lists the known [[Starlet]] I/O registers. Much of this info comes from Segher & tmbinc's private notes.
This page lists the known [[Starlet]] I/O registers. Much of this info comes from Segher & tmbinc's private notes.
−== IO Memory ==
== IO Memory ==