40
edits
Changes
Add memory overview table.
Line 2:
Line 2:
== Memory map ==
== Memory map ==
+
+{| style="border-collapse: collapse; padding: 0.2em 0.2em 0.2em 0.2em;"
+|- style="background-color: #ddd;"
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #ddd;" | '''Start Address'''
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #ddd;" | '''End Address'''
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #ddd;" | '''Physical Address'''
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #ddd;" | '''Size'''
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #ddd;" | '''Description'''
+
+|- style="background-color: #ddd;"
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x00000000
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x017FFFFF
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x00000000
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 24 MB
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | MEM1 Memory (Cached)
+
+|- style="background-color: #ddd;"
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x10000000
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x13FFFFFF
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x10000000
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 64 MB
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | MEM2 Memory (Cached)
+
+|- style="background-color: #ddd;"
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x0D000000
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" |
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" |
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" |
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | Hardware Registers (shared with the Broadway)
+
+|- style="background-color: #ddd;"
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x0D800000
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" |
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" |
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" |
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | Hardware Registers (Starlet private)
+
+|- style="background-color: #ddd;"
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0xFFFE0000
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0xFFFFFFFF
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" |
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" |
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | Internal SRAM
+|}
I/O is at x'0d80_0000 (Starlet private) and x'0d00_0000 (shared with the Broadway). That is to say, the contents of 0x0d8x are selectively mirrored to 0x0d0x. This may change depending on some of the registers (e.g. when MIOS is active).
I/O is at x'0d80_0000 (Starlet private) and x'0d00_0000 (shared with the Broadway). That is to say, the contents of 0x0d8x are selectively mirrored to 0x0d0x. This may change depending on some of the registers (e.g. when MIOS is active).