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−
[[Image:Wii_hw_diagram.png]]
+[[Image:Wii_hw_diagram.png|thumb|right|Wii hardware diagram]]
+==Wii specs==
===CPU===
===CPU===
* IBM '[http://en.wikipedia.org/wiki/Broadway_%28microprocessor%29 Broadway]' 90 nm based on IBM's Power architecture.
* IBM '[http://en.wikipedia.org/wiki/Broadway_%28microprocessor%29 Broadway]' 90 nm based on IBM's Power architecture.
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*One floating point unit (FPU) (supports single precision (32-bit) and double precision (64-bit))
*One floating point unit (FPU) (supports single precision (32-bit) and double precision (64-bit))
*The FPU supports paired single floating point (FP/PS)
*The FPU supports paired single floating point (FP/PS)
−*The FPU supports paired single multiply add (ps_madd). Most FP/PS instructions can be issued in
+*The FPU supports paired single multiply add (ps_madd). Most FP/PS instructions can be issued in each cycle and completed in three cycles.
−each cycle and completed in three cycles.
*Fixed-point to floating-point conversion can be performed at the same time as FPU register load and store, with no loss in performance.
*Fixed-point to floating-point conversion can be performed at the same time as FPU register load and store, with no loss in performance.
*The branch unit supports static branch prediction and dynamic branch prediction.
*The branch unit supports static branch prediction and dynamic branch prediction.