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→VData Encoding: Found reference VHDL code which implies the encoding
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|64
|64
|VData 0
|VData 0
+|}
+
+== VData Encoding ==
+<!--
+Note: All of this section is based on interpreting the VHDL code of gcvideo, which has support for the Wii. I'm a programmer who took one VHDL class, so there's likely quite a few inaccuracies but the general gist should be correct. I'm unable to verify it with a logic analyzer because mine only goes to maybe 10 MHz.
+
+There's some code there which talks about switching between a 15 kHz and 30 kHz video mode, but as written it should only ever select 30 kHz.
+-->
+[[File:GPU raw timing.png|thumb|right|Raw timing diagram]]
+The VData pins are an 8-bit parallel bus with a 54 MHz rising edge clock and "clock select" (CSel) line. The bus sends one byte per clock tick, with VData0 being the LSB and VData7 being the MSB. The bus interleaves Y, CbCr, and flags clocked to CSel edge. When CSel changes (both rising and falling), the first byte is Y. A Y value of 0 indicates blanking and is followed by a flag byte. Otherwise, the next byte is CbCr.{{ref|{{cite web|url=https://github.com/ikorb/gcvideo/blob/main/HDL/gcvideo_dvi/src/gcdv_decoder.vhd|title=gcdv_decoder.vhd}}}}
+
+The flag byte is divided as follows (big endian):
+{|class=wikitable
+!Bit
+!Name
+|-
+|7
+|CSync (active low)
+|-
+|6
+|IsEvenField
+|-
+|5
+|VSync (active low)
+|-
+|4
+|HSync (active low)
+|-
+|3
+|(unused)
+|-
+|2
+|(unused)
+|-
+|1
+|IsPAL
+|-
+|0
+|IsProgressive
|}
|}
== References ==
== References ==
{{references}}
{{references}}