Changes

|ENA|Enable en/decryption. If clear, the data is copied straight from source to destination without change (useful as a DMA copy engine?).

|ENA|Enable en/decryption. If clear, the data is copied straight from source to destination without change (useful as a DMA copy engine?).

|DEC|Set to decrypt, clear to encrypt

|DEC|Set to decrypt, clear to encrypt

|IV|If set, use the supplied IV. If clear, chain from last command (continue CBC mode).

|IV|If set, chain from last command (continue CBC mode). If clear, use the supplied IV.

|DATALEN|Number of 16-byte blocks to process, minus one. 0 means one block.

|DATALEN|Number of 16-byte blocks to process, minus one. 0 means one block.

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This register implements a FIFO that accepts the AES key. A sequence of four 32-bit writes will set the AES key (starting with the leftmost 32-bit word).

This register implements a FIFO that accepts the AES key. A sequence of four 32-bit writes will set the AES key (starting with the leftmost 32-bit word).

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{{regsimple | AES_KEY | addr = 0x0d02000c | bits = 32 | access = W }}

{{regsimple | AES_IV | addr = 0x0d02000c | bits = 32 | access = W }}

This register implements a FIFO that accepts the AES IV. A sequence of four 32-bit writes will set the AES IV (starting with the leftmost 32-bit word).

This register implements a FIFO that accepts the AES IV. A sequence of four 32-bit writes will set the AES IV (starting with the leftmost 32-bit word).

Set the IV bit in the [[#AES_CTRL|AES_CTRL]] register to restart the CBC encryption using this IV instead of using the last encrypted block.

Clear the IV bit in the [[#AES_CTRL|AES_CTRL]] register to restart the CBC encryption using this IV instead of using the last encrypted block.