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Hardware/External Interface (view source)

Revision as of 23:17, 9 March 2025

6,626 bytes added ,  9 March
→‎Register List: fix duplicate interrupt name
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| ppc = Partial
 
| ppc = Partial
 
| arm = Full
 
| arm = Full
−
| base = 0x0c006800
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| base = 0x0d806800
 
| len = 0x80
 
| len = 0x80
 
| bits = 32
 
| bits = 32
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{{hwstub}}
 
{{hwstub}}
 
{{yagcd}}
 
{{yagcd}}
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The External Interface (EXI) is an interface to communicate with external devices like the Gamecube memory cards slots, which can be used for memory cards, usb gecko, sdgecko, or nintendo's waikiki's debug adaptor.
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On the Wii, the PowerPC's reset vector (0xfff00000) is mapped to memory within the EXI while on the GameCube this was mapped to the IPL masked bootrom. Since there is no IPL in the Wii ROM, this memory is written to by [[IOS]] when it bootstraps the [[Broadway]].
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== Register List ==
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{{reglist|EXI}}
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{{rla|0x0d806800|32|EXI_CSR|EXI Channel 0 Parameter Register (Status?)}}
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{{rla|0x0d806804|32|EXI_MAR|EXI Channel 0 DMA Start Address}}
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{{rla|0x0d806808|32|EXI_LENGTH|EXI EXI Channel 0 DMA Transfer Length}}
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{{rla|0x0d80680c|32|EXI_CR|EXI Channel 0 Control Register}}
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{{rla|0x0d806810|32|EXI_DATA|EXI Channel 0 Immediate Data}}
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{{rla|0x0d806814|32|EXI_CSR|EXI Channel 1 Parameter Register (Status?)}}
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{{rla|0x0d806818|32|EXI_MAR|EXI Channel 1 DMA Start Address}}
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{{rla|0x0d80681c|32|EXI_LENGTH|EXI EXI Channel 1 DMA Transfer Length}}
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{{rla|0x0d806820|32|EXI_CR|EXI Channel 1 Control Register (Status?)}}
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{{rla|0x0d806824|32|EXI_DATA|EXI Channel 1 Immediate Data}}
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{{rla|0x0d806828|32|EXI_CSR|EXI Channel 2 Parameter Register (Status?)}}
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{{rla|0x0d80682c|32|EXI_MAR|EXI Channel 2 DMA Start Address}}
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{{rla|0x0d806830|32|EXI_LENGTH|EXI EXI Channel 2 DMA Transfer Length}}
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{{rla|0x0d806834|32|EXI_CR|EXI Channel 2 Control Register (Status?)}}
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{{rla|0x0d806838|32|EXI_DATA|EXI Channel 2 Immediate Data}}
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|}
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{{reg32 | EXI_CSR| addr = | hifields = 1 | lofields = 11 |
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|16|
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| |
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|          ||
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|2|1        |1    |1      |1          |3  |3  |1    |1        |1      |1          |
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| |R/W      |R/W  |R/W    |R/W        |R/W |R/W |R/W  |R/W      |R/W    |R/W        |
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| |ROMDIS  |EXT  |EXTINT |EXTINTMASK |CS  |CLK |TCINT |TCINTMASK |EXIINT |EXIINTMASK  ||
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}}
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This register at least controls the boot0 memory mapping and DSK PLL source.
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{{regdesc
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|ROMDIS|on GC it masked the ipl, Unknown purpose on the wii
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|EXT|Device Connected Bit (R) 1 if a device is connected on the specific channel
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|EXTINT|External Insertion Interrupt Status
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This interrupt indicates than an external EXI device has been removed from channel x.
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To check whether the device has been inserted or removed, check the EXICPR bit. When this bit is set, the channel's expansion EXI interface outputs go to high.
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* When read 1 or 0 indicates if interrupt is requested
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* When 1 is written to this register, it clears the interrupt
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|EXTINTMASK|EXT Interrupt Mask (1 - enable, 0 - disable) (*5)
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|CS|devices selected on this channel, each bit selecting one device.
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Only one of these three bits can be set to signify which device number has been selected on a specific channel.
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|CLK|used frequency
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<source>
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000 = 0.84375MHz
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001 = 1.6875MHz
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010 = 3.375MHz
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011 = 6.75MHz
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100 = 13.5MHz
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101 = 27MHz
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110 = 54MHz
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111 = reserved (0.84375MHz)
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</source>
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|TCINT|Transfer Complete Interrupt Status
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* When read 1 or 0 indicates if interrupt is requested
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* When 1 is written to this register, it clears the interrupt
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|TCINTMASK|Transfer complete interrupt mask (1 - enable, 0 - disable).
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Interrupt masking prevents the interrupt from being sent to the main processor, but does not affect the assertion of TCINT
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|EXIINT|Interrupt Status
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* When read 1 or 0 indicates if interrupt is requested
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* When 1 is written to this register, it clears the interrupt
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|EXIINTMASK|EXI interrupt mask (1 - enable, 0 - disable)
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}}
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{{reg32 | EXIMAR| addr = | hifields = 1 | lofields = 2 |
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|16  |
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|R/W  |
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|Data ||
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|11  |5|
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|R/W  | |
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|Data | ||
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}}
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Physical Startaddress for DMA transfer. Must be aligned to 32 byte boundary.
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{{reg32 | EXI_LENGTH| addr = | hifields = 1 | lofields = 2 |
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|16  |
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|R/W  |
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|Data ||
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|11  |5|
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|R/W  | |
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|Data | ||
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}}
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Size of DMA transfer data in bytes. bits 0-4 are always zero (which means the size is 32 byte aligned)
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{{reg32 | EXI_CR| addr = | hifields = 1 | lofields = 5 |
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|16 |
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| |
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| ||
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|10 |2  |2  |1  |1      |
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|  |TLEN|RW |DMA |TSTART |
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|  |R/W |R/W|R/W |R/W    ||
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}}
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{{regdesc
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|TLEN|(data length-1) for immediate mode
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<source>
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00 = 1 byte
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01 = 2 byte
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10 = 3 byte
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11 = 4 byte
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</source>
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|RW|transfer type. all immediate transfers are effectively read and write.
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<source>
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00 = read
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01 = write
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10 = read and write, invalid for DMA
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11 = undefined
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</source>
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|DMA|transfer mode (0 - immediate, 1 - DMA)
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|TSTART|set, to start transfer. will be cleared after transfer completed.
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}}
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{{reg32 | EXI_DATA| addr = | hifields = 1 | lofields = 1 |
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|16  |
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|R/W |
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|Data||
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|16  |
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|R/W |
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|Data||
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}}
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Data for read / write immediate operations (up to 4 bytes long).
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== EXI boot vector ==
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As mentioned, there is small amount of memory in the EXI that is used as the PowerPC reset vector. 
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IOS's function to initialize the EXI reset vector has 2 default boot vectors depending on the parameters, but a custom boot vector is used by the <code>IOS_StartPPC</code>  [[IOS/Syscalls|syscall]]. It is 0x40 bytes in size and is accessed through different addresses depending where you are reading from.
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{| class="wikitable"
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|-
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! Source
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! Start Address
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! End Address
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|-
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| EXI
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| 0x0d806840
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| 0x0d806880
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|-
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| PPC
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| 0xfff00100
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| 0xfff00140
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|-
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|}
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=== IOS_StartPPC vector ===
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<source>
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fff00100    3c 60 00 00    lis  r3, 0
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fff00104    60 63 34 00    ori  r3, r3, 0x3400
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fff00108    7c 7a 03 a6    mtspr SRR0, r3
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fff0010c    38 60 00 00    li    r3, 0
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fff00110    7c 7b 03 a6    mtspr SRR1, r3
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fff00114    4c 00 00 64    rfi
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</source>
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=== Default vector (with HID4 initialization) ===
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<source>
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fff00100    7c 63 1a 78    xor  r3, r3, r3
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fff00104    64 63 d7 b0    oris  r3, r3, 0xd7b0
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fff00108    7c 73 fb a6    mtspr HID4, r3
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fff0010c    4c 00 01 2c    isync
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fff00110    3c 40 00 00    lis  r2, 0x0
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fff00114    60 42 01 00    ori  r2, r2, 0x100
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fff00118    7c 5a 03 a6    mtspr SRR0, r2
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fff0011c    38 a0 00 00    li    r5, 0
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fff00120    7c bb 03 a6    mtspr SRR1, r5
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fff00124    4c 00 00 64    rfi
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fff00128    60 00 00 00    nop
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fff0012c    60 00 00 00    nop
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fff00130    60 00 00 00    nop
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</source>
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=== Default vector (without HID4 initialization) ===
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<source>
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fff00100    7c 63 1a 78    xor  r3, r3, r3
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fff00104    7c 73 fb a6    mtspr HID4, r3
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fff00108    4c 00 01 2c    isync
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fff0010c    3c 40 00 00    lis  r2, 0
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fff00110    60 42 01 00    ori  r2, r2, 0x100
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fff00114    7c 5a 03 a6    mtspr SRR0, r2
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fff00118    38 a0 00 00    li    r5, 0
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fff0010c    7c bb 03 a6    mtspr SRR1, r5
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fff00120    4c 00 00 64    rfi
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fff00124    60 00 00 00    nop
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fff00128    60 00 00 00    nop
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fff0012c    60 00 00 00    nop
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</source>
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[[Category:Official hardware]]
Flacs
24

edits

Retrieved from "https://wiibrew.org/wiki/Special:MobileDiff/44121...120814"