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Hardware/External Interface (view source)

Revision as of 23:17, 9 March 2025

1,919 bytes added ,  9 March
→‎Register List: fix duplicate interrupt name
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{{yagcd}}
 
{{yagcd}}
   −
the External Interface (EXI) is an interface to communicate with external devices like the Gamecube memory cards slots, which can be used for memory cards, usb gecko, sdgecko, or nintendo's waikiki's debug adaptor.
+
The External Interface (EXI) is an interface to communicate with external devices like the Gamecube memory cards slots, which can be used for memory cards, usb gecko, sdgecko, or nintendo's waikiki's debug adaptor.
−
On the wii, the PowerPC's reset vector (0xfff00000) is mapped to memory within the EXI while on the gamecube this was mapped to the IPL masked bootrom.
  −
Since there is no IPL on the wii, this memory is written to by [[IOS]] when it bootstraps the [[Broadway]].
     −
== Registry List ==
+
On the Wii, the PowerPC's reset vector (0xfff00000) is mapped to memory within the EXI while on the GameCube this was mapped to the IPL masked bootrom. Since there is no IPL in the Wii ROM, this memory is written to by [[IOS]] when it bootstraps the [[Broadway]].
 +
 
 +
== Register List ==
 
{{reglist|EXI}}
 
{{reglist|EXI}}
−
{{rla|0x0d806800|32|EXI0_CSR|EXI Channel 0 Parameter Register (Status?)}}
+
{{rla|0x0d806800|32|EXI_CSR|EXI Channel 0 Parameter Register (Status?)}}
−
{{rla|0x0d806800|32|EXI0_MAR|EXI Channel 0 DMA Start Address}}
+
{{rla|0x0d806804|32|EXI_MAR|EXI Channel 0 DMA Start Address}}
−
{{rla|0x0d806800|32|EXI0_LENGTH|EXI EXI Channel 0 DMA Transfer Length}}
+
{{rla|0x0d806808|32|EXI_LENGTH|EXI EXI Channel 0 DMA Transfer Length}}
−
{{rla|0x0d806800|32|EXI0_CR|EXI Channel 0 Control Register}}
+
{{rla|0x0d80680c|32|EXI_CR|EXI Channel 0 Control Register}}
−
{{rla|0x0d806810|32|EXI0_DATA|EXI Channel 0 Immediate Data}}
+
{{rla|0x0d806810|32|EXI_DATA|EXI Channel 0 Immediate Data}}
−
{{rla|0x0d806814|32|EXI1_CSR|EXI Channel 1 Parameter Register (Status?)}}
+
{{rla|0x0d806814|32|EXI_CSR|EXI Channel 1 Parameter Register (Status?)}}
−
{{rla|0x0d806818|32|EXI1_MAR|EXI Channel 1 DMA Start Address}}
+
{{rla|0x0d806818|32|EXI_MAR|EXI Channel 1 DMA Start Address}}
−
{{rla|0x0d80681c|32|EXI1_LENGTH|EXI EXI Channel 1 DMA Transfer Length}}
+
{{rla|0x0d80681c|32|EXI_LENGTH|EXI EXI Channel 1 DMA Transfer Length}}
−
{{rla|0x0d806820|32|EXI0_CR|EXI Channel 1 Control Register (Status?)}}
+
{{rla|0x0d806820|32|EXI_CR|EXI Channel 1 Control Register (Status?)}}
−
{{rla|0x0d806824|32|EXI0_DATA|EXI Channel 1 Immediate Data}}
+
{{rla|0x0d806824|32|EXI_DATA|EXI Channel 1 Immediate Data}}
−
{{rla|0x0d806828|32|EXI2_CSR|EXI Channel 2 Parameter Register (Status?)}}
+
{{rla|0x0d806828|32|EXI_CSR|EXI Channel 2 Parameter Register (Status?)}}
−
{{rla|0x0d80682c|32|EXI2_MAR|EXI Channel 2 DMA Start Address}}
+
{{rla|0x0d80682c|32|EXI_MAR|EXI Channel 2 DMA Start Address}}
−
{{rla|0x0d806830|32|EXI2_LENGTH|EXI EXI Channel 2 DMA Transfer Length}}
+
{{rla|0x0d806830|32|EXI_LENGTH|EXI EXI Channel 2 DMA Transfer Length}}
−
{{rla|0x0d806834|32|EXI2_CR|EXI Channel 2 Control Register (Status?)}}
+
{{rla|0x0d806834|32|EXI_CR|EXI Channel 2 Control Register (Status?)}}
−
{{rla|0x0d806838|32|EXI2_DATA|EXI Channel 2 Immediate Data}}
+
{{rla|0x0d806838|32|EXI_DATA|EXI Channel 2 Immediate Data}}
 
|}
 
|}
   −
=== Parameter Register ===
     −
{{reg32 | EXIX_CSR | addr = | hifields = 1 | lofields = 9 |
+
 
 +
{{reg32 | EXI_CSR| addr = | hifields = 1 | lofields = 11 |
 
|16|
 
|16|
 
| |
 
| |
 
|          ||
 
|          ||
 
|2|1        |1    |1      |1          |3  |3  |1    |1        |1      |1          |
 
|2|1        |1    |1      |1          |3  |3  |1    |1        |1      |1          |
 +
| |R/W      |R/W  |R/W    |R/W        |R/W |R/W |R/W  |R/W      |R/W    |R/W        |
 +
| |ROMDIS  |EXT  |EXTINT |EXTINTMASK |CS  |CLK |TCINT |TCINTMASK |EXIINT |EXIINTMASK  ||
 
}}
 
}}
 
This register at least controls the boot0 memory mapping and DSK PLL source.
 
This register at least controls the boot0 memory mapping and DSK PLL source.
 
{{regdesc
 
{{regdesc
−
|ROMDIS|(EXI0 only) 1: rom de-scramble logic disabled (*1)
+
|ROMDIS|on GC it masked the ipl, Unknown purpose on the wii
 
|EXT|Device Connected Bit (R) 1 if a device is connected on the specific channel
 
|EXT|Device Connected Bit (R) 1 if a device is connected on the specific channel
 
|EXTINT|External Insertion Interrupt Status
 
|EXTINT|External Insertion Interrupt Status
 +
This interrupt indicates than an external EXI device has been removed from channel x.
 +
To check whether the device has been inserted or removed, check the EXICPR bit. When this bit is set, the channel's expansion EXI interface outputs go to high.
 
* When read 1 or 0 indicates if interrupt is requested
 
* When read 1 or 0 indicates if interrupt is requested
 
* When 1 is written to this register, it clears the interrupt
 
* When 1 is written to this register, it clears the interrupt
 
|EXTINTMASK|EXT Interrupt Mask (1 - enable, 0 - disable) (*5)
 
|EXTINTMASK|EXT Interrupt Mask (1 - enable, 0 - disable) (*5)
−
|CS|devices selected on this channel, each bit selecting one device. (*)
+
|CS|devices selected on this channel, each bit selecting one device.  
 +
Only one of these three bits can be set to signify which device number has been selected on a specific channel.
 
|CLK|used frequency
 
|CLK|used frequency
 
<source>
 
<source>
−
000 = 1MHz
+
000 = 0.84375MHz
−
001 = 2MHz
+
001 = 1.6875MHz
−
010 = 4MHz
+
010 = 3.375MHz
−
011 = 8MHz
+
011 = 6.75MHz
−
100 = 16MHz
+
100 = 13.5MHz
−
101 = 32MHz
+
101 = 27MHz
−
110 = reserved
+
110 = 54MHz
−
111 = reserved
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111 = reserved (0.84375MHz)
 
</source>
 
</source>
 
|TCINT|Transfer Complete Interrupt Status
 
|TCINT|Transfer Complete Interrupt Status
 
* When read 1 or 0 indicates if interrupt is requested
 
* When read 1 or 0 indicates if interrupt is requested
 
* When 1 is written to this register, it clears the interrupt
 
* When 1 is written to this register, it clears the interrupt
−
|TCINTMASK|Transfer complete interrupt mask (1 - enable, 0 - disable) (*2)
+
|TCINTMASK|Transfer complete interrupt mask (1 - enable, 0 - disable).
−
|EXTINT|Interrupt Status
+
Interrupt masking prevents the interrupt from being sent to the main processor, but does not affect the assertion of TCINT
 +
|EXIINT|Interrupt Status
 
* When read 1 or 0 indicates if interrupt is requested
 
* When read 1 or 0 indicates if interrupt is requested
 
* When 1 is written to this register, it clears the interrupt
 
* When 1 is written to this register, it clears the interrupt
−
|EXTINTMASK|EXI interrupt mask (1 - enable, 0 - disable)
+
|EXIINTMASK|EXI interrupt mask (1 - enable, 0 - disable)
 +
}}
 +
 
 +
{{reg32 | EXIMAR| addr = | hifields = 1 | lofields = 2 |
 +
|16  |
 +
|R/W  |
 +
|Data ||
 +
|11  |5|
 +
|R/W  | |
 +
|Data | ||
 +
}}
 +
Physical Startaddress for DMA transfer. Must be aligned to 32 byte boundary.
 +
 
 +
 
 +
{{reg32 | EXI_LENGTH| addr = | hifields = 1 | lofields = 2 |
 +
|16  |
 +
|R/W  |
 +
|Data ||
 +
|11  |5|
 +
|R/W  | |
 +
|Data | ||
 +
}}
 +
Size of DMA transfer data in bytes. bits 0-4 are always zero (which means the size is 32 byte aligned)
 +
 
 +
 
 +
{{reg32 | EXI_CR| addr = | hifields = 1 | lofields = 5 |
 +
|16 |
 +
| |
 +
| ||
 +
|10 |2  |2  |1  |1      |
 +
|  |TLEN|RW |DMA |TSTART |
 +
|  |R/W |R/W|R/W |R/W    ||
 +
}}
 +
{{regdesc
 +
|TLEN|(data length-1) for immediate mode
 +
<source>
 +
00 = 1 byte
 +
01 = 2 byte
 +
10 = 3 byte
 +
11 = 4 byte
 +
</source>
 +
|RW|transfer type. all immediate transfers are effectively read and write.
 +
<source>
 +
00 = read
 +
01 = write
 +
10 = read and write, invalid for DMA
 +
11 = undefined
 +
</source>
 +
|DMA|transfer mode (0 - immediate, 1 - DMA)
 +
|TSTART|set, to start transfer. will be cleared after transfer completed.
 
}}
 
}}
 +
 +
 +
{{reg32 | EXI_DATA| addr = | hifields = 1 | lofields = 1 |
 +
|16  |
 +
|R/W |
 +
|Data||
 +
|16  |
 +
|R/W |
 +
|Data||
 +
}}
 +
Data for read / write immediate operations (up to 4 bytes long).
    
== EXI boot vector ==
 
== EXI boot vector ==
−
   
As mentioned, there is small amount of memory in the EXI that is used as the PowerPC reset vector.   
 
As mentioned, there is small amount of memory in the EXI that is used as the PowerPC reset vector.   
   −
IOS's function to initialize the EXI reset vector has 2 default boot vectors depending on the parameters, but a custom boot vector is used by the <code>IOS_StartPPC</code>  [[IOS/Syscalls|syscall]].
+
IOS's function to initialize the EXI reset vector has 2 default boot vectors depending on the parameters, but a custom boot vector is used by the <code>IOS_StartPPC</code>  [[IOS/Syscalls|syscall]]. It is 0x40 bytes in size and is accessed through different addresses depending where you are reading from.
   −
{| class="wikitable
+
{| class="wikitable"
 
|-
 
|-
 +
! Source
 
! Start Address
 
! Start Address
 
! End Address
 
! End Address
−
! Size
  −
! Description
   
|-
 
|-
 +
| EXI
 
| 0x0d806840
 
| 0x0d806840
 
| 0x0d806880
 
| 0x0d806880
−
| 0x40
+
|-
−
| PPC Reset vector
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| PPC
 +
| 0xfff00100
 +
| 0xfff00140
 
|-
 
|-
 
|}
 
|}
Flacs
24

edits

Retrieved from "https://wiibrew.org/wiki/Special:MobileDiff/118286...120814"