Changes

* For the DDR BIST, MEM_BIST_ADDR and MEM_BIST_DATA

* For the DDR BIST, MEM_BIST_ADDR and MEM_BIST_DATA

* For the DPERF registers, presumably MEM_PERF and MEM_PERF_READ are involved {{check}}

* For the DPERF registers, presumably MEM_PERF and MEM_PERF_READ are involved {{check}}

* MEM_ARB_EXADDR and MEM_ARB_EXCMD might hint at the existence of some other yet-undocumented register space (perhaps for AHB arbitration) {{check}}

* MEM_ARB_EXADDR and MEM_ARB_EXCMD are used during DRAM initialization for Mode Register Set programming (the layout is probably vendor-specific).

Although the memory controller registers are actually mapped and available to ARM starting at 0x0d8b4200, some [all?] of the indirect accesses are

Although the memory controller registers are actually mapped and available to ARM starting at 0x0d8b4200, some [all?] of the indirect accesses are