|Access size||32 bits|
|Byte order||Big Endian|
The Hollywood chipset includes 24 general purpose I/O lines with interrupt capability. Two sets of registers are provided, and the Broadway only has access to one set. This set accesses a configurable subset of the IO pins, which the Starlet can select.
|0x0d8000c0||32||HW_GPIOB_OUT||GPIO Outputs (Broadway access)|
|0x0d8000c4||32||HW_GPIOB_DIR||GPIO Direction (Broadway access)|
|0x0d8000c8||32||HW_GPIOB_IN||GPIO Inputs (Broadway access)|
|0x0d8000cc||32||HW_GPIOB_INTLVL||GPIO Interrupt Levels (Broadway access)|
|0x0d8000d0||32||HW_GPIOB_INTFLAG||GPIO Interrupt Flags (Broadway access)|
|0x0d8000d4||32||HW_GPIOB_INTMASK||GPIO Interrupt Masks (Broadway access)|
|0x0d8000d8||32||HW_GPIOB_STRAPS||GPIO Straps (Broadway access)|
|0x0d8000dc||32||HW_GPIO_ENABLE||GPIO Enable (Starlet only)|
|0x0d8000e0||32||HW_GPIO_OUT||GPIO Outputs (Starlet only)|
|0x0d8000e4||32||HW_GPIO_DIR||GPIO Direction (Starlet only)|
|0x0d8000e8||32||HW_GPIO_IN||GPIO Inputs (Starlet only)|
|0x0d8000ec||32||HW_GPIO_INTLVL||GPIO Interrupt Levels (Starlet only)|
|0x0d8000f0||32||HW_GPIO_INTFLAG||GPIO Interrupt Flags (Starlet only)|
|0x0d8000f4||32||HW_GPIO_INTMASK||GPIO Interrupt Masks (Starlet only)|
|0x0d8000f8||32||HW_GPIO_STRAPS||GPIO Straps (Starlet only)|
|0x0d8000fc||32||HW_GPIO_OWNER||GPIO Owner Select (Starlet only)|
"Direction" and "PPC access" are based on typical values that IOS assigns to the HW_GPIO_OWNER and HW_GPIO_DIR registers.
|0||0x000001||IN||No||POWER||Power button input (pulse width limited; will not detect a held-down state).|
|1||0x000002||OUT||No||SHUTDOWN||Output high to turn system off (Power LED = red).|
|2||0x000004||OUT||No||FAN||Fan power, active high.|
|3||0x000008||OUT||No||DC_DC||DC/DC converter power, active high (powers the Broadway?[check]). When off, also triggers the Yellow power LED.|
|4||0x000010||OUT||No||DI_SPIN||DI spinup disable. If clear, the drive attempts to spin up a disc when reset (if there is one in the drive). If set, the drive ignores a present disc when reset.|
|5||0x000020||OUT||Yes||SLOT_LED||Blue disc slot LED, active high.|
|6||0x000040||IN||No||EJECT_BTN||Eject button (pulse width limited). Button press will also trigger the drive directly.|
|7||0x000080||IN||Yes||SLOT_IN||Disc slot optical detector. High if disc in drive, disc being inserted, or disc still in slot after eject. Temporarily low when inserting or exiting when the hole in the middle of the disc passes above the sensor.|
|8||0x000100||OUT||Yes||SENSOR_BAR||Sensor bar, active high.|
|9||0x000200||OUT||Yes||DO_EJECT||Pulse high to trigger a DI eject from software.|
|10||0x000400||OUT||No||EEP_CS||SEEPROM Chip Select.|
|12||0x001000||OUT||No||EEP_MOSI||Data to SEEPROM.|
|13||0x002000||IN||No||EEP_MISO||Data from SEEPROM.|
|14||0x004000||OUT||Yes||AVE_SCL||A/V Encoder I²C Clock.|
|15||0x008000||I/O||Yes||AVE_SDA||A/V Encoder I²C Data (has an external pull-up, so you should only drive it low).|
|16||0x010000||OUT||No||DEBUG0||Debug Testpoint TP221.|
|17||0x020000||OUT||No||DEBUG1||Debug Testpoint TP222.|
|18||0x040000||OUT||No||DEBUG2||Debug Testpoint TP223.|
|19||0x080000||OUT||No||DEBUG3||Debug Testpoint TP224.|
|20||0x100000||OUT||No||DEBUG4||Debug Testpoint TP225.|
|21||0x200000||OUT||No||DEBUG5||Debug Testpoint TP226.|
|22||0x400000||OUT||No||DEBUG6||Debug Testpoint TP219.|
|23||0x800000||OUT||No||DEBUG7||Debug Testpoint TP220.|
The bits of this register indicate whether specific GPIO pins are enabled. The typical value is 0xFFFFFF, to enable all pins.
This register contains the output value for all pins. These only take effect if the pin is configured as an output.
A '1' bit for a pin indicates that it will behave as an output (drive), while a '0' bit tristates the pin and it becomes a high-impedance input.
This register can be read to obtain the current input value of the GPIO pins.
Configures the pin state that causes an interrupt. If a bit is set in this register, the pin causes an interrupt when high. A zero causes the opposite behavior.
Bits in this register indicate which pins have triggered their interrupt flags. Write one to clear a bit back to zero. The bits can only be cleared if the pin is in the idle state: if the pin state equals the value in the HW_GPIO_INTLVL register, then the corresponding bit in HW_GPIO_INTFLAG will be stuck at one until the pin state reverts or the value in HW_GPIO_INTLVL is inverted. Once the pin is idle, the bits in this register may be cleared by writing one to them.
Only the bits set in this register propagate their interrupts to the master Hollywood GPIO interrupt (#11). All other pin interrupts are ignored, although the interrupt state can still be queried and cleared in HW_GPIO_INTFLAG. Note: Pins configured for Broadway access do not generate Hollywood IRQ #11. Instead, they generate Hollywood IRQ #10. In other words, the IRQ generation logic for #11 is HW_GPIO_INTMASK & HW_GPIO_INTFLAG & ~HW_GPIO_OWNER.
This register appears to contain the input state at some point in time, possibly power-on or interrupt or something like that. Writes do not seem possible.
This register configures which pins can be controlled by the HW_GPIOB registers. A one bit configures the pin for control via the HW_GPIOB registers, which lets it be accessed by the Broadway. A zero bit restricts access to the HW_GPIO registers, which are Starlet-only. The HW_GPIO registers always have read access to all pins, but any writes (changes) must go through the HW_GPIOB registers if the corresponding bit is set in the HW_GPIO_OWNER register.
These registers operate identically to their HW_GPIO counterparts above, but they only control the pins which have their respective HW_GPIO_OWNER bits set to 1. They can be accessed by the Broadway as well as the Starlet. The master interrupt feeds to the Hollywood GPIOB interrupt (#10). The generation logic would be HW_GPIOB_INTFLAG & HW_GPIOB_INTMASK, with an implicit AND with HW_GPIO_OWNER since the GPIOB registers are already masked with the HW_GPIO_OWNER register.
When switching owners, copying of the data is not necessary. For example, if pin 0 has certain configuration in the HW_GPIO registers, and that bit is then set in the HW_GPIO_OWNER register, those settings will immediately be visible in the HW_GPIOB registers. There is only one set of data registers, and the HW_GPIO_OWNER register just controls the access that the HW_GPIOB registers have to that data.