Hardware/GX

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Pixel Engine
Access
BroadwayFull
StarletNone
Registers
Base0x0c001000
Length0x100
Access size32 bits
Byte orderBig Endian
IRQs
Broadway9,10
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Contents

GX FIFO

Graphics processor commands can be 8bit or 32bit, but they must be sent padded to 32bit. The CPU has a 32-bit FIFO accessed through the WGPIPE register at 0xcc008000 that will automatically pack data for you. All sorts of graphics data (vertices, primitives, etc) are sent through the FIFO.

The FIFO is a ring buffer in main memory. It is similar that it can be placed anywhere in main memory. One needs to initialize CP registers to describe the FIFO. Afterwards, all communications to the CP (including those forwarded to other units) are performed through the FIFO.

BP (blitting processor) registers

The BP registers are accessed by writing a 8-bit value of 0x61 to the FIFO, followed by 32 bit value. This value is a bit weird - the high 8 bits are the register, and the low 24 bits are the register value. More information on the BP can be found here.

CP (command processor) registers

The (internal, there are other CP registers mapped to main memory) CP registers are accessed by writing a 8-bit 0x08 to the FIFO, followed by 8 bits of something and then 32 bits of something. More information on the CP can be found here.

XF (transform unit) registers

The XF registers are accessed by first writing an 8-bit number of 0x10 to the FIFO, then a 32 bit value whose lower 16 bits are the address, and the upper 16 bits are the number of addresses to write to - 1. Following is one or more 32 bit datas. More info on the XF can be found here.

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