Difference between revisions of "Hardware/GX/Command Processor"
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(Created CP page.) |
(Added CP infobox, and hwstub and yagcd templates) |
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| + | {{Infobox MMIO | ||
| + | | title = Command Processor | ||
| + | | ppc = Full | ||
| + | | base = 0x0c000000 | ||
| + | | len = 0x80 | ||
| + | | bits = 16 | ||
| + | | ppcirq = 11 | ||
| + | }} | ||
| + | {{hwstub}} | ||
| + | {{yagcd}} | ||
The Command Processor is a part of the Wii's GX system, and is responsible for handling all of the commands that draw to the EFB. | The Command Processor is a part of the Wii's GX system, and is responsible for handling all of the commands that draw to the EFB. | ||
== CP (command processor) Registers == | == CP (command processor) Registers == | ||
Revision as of 00:39, 12 July 2010
| Command Processor | |
| Access | |
|---|---|
| Broadway | Full |
| Starlet | None |
| Registers | |
| Base | 0x0c000000 |
| Length | 0x80 |
| Access size | 16 bits |
| Byte order | Big Endian |
| IRQs | |
| Broadway | 11 |
| This Hardware-related article is a stub. You can help WiiBrew by expanding it. |
| This article may be improved with information from Yet Another GameCube Documentation. You can help WiiBrew by expanding this article with the information and wikifying it. |
The Command Processor is a part of the Wii's GX system, and is responsible for handling all of the commands that draw to the EFB.
CP (command processor) Registers
| CP_FIFO_STATUS (0xCC000000) | ||||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | U | R | R | R | R | R | ||||||||||
| Field | BPInt | CmdIdle | RdIdle | UF | OF | |||||||||||
| Field | Description |
| BPInt | Indicates status of Blitting Processor interrupt? |
| CmdIdle | 1: CP is not doing anything |
| RdIdle | 1: CP is not reading anything (??) |
| UF | FIFO underflow (Determined by watermark registers? |
| OF | FIFO overflow ("") |
| CP_CONTROL (0xCC000002) | ||||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | U | R/W | R/W | R/W | R/W | R/W | R/W | |||||||||
| Field | BPE | GPLE | UFInt | OFInt | CPInt | FIFOE | ||||||||||
| Field | Description |
| BPE | breakpoint enable (default 0) |
| GPLE | FIFO link enable (YAGCD says CP->PE?) (default 1) |
| UFInt | FIFO underflow interrupt (default 0) |
| OFInt | FIFO overflow interrupt (default 1) |
| CPInt | Command Processor interrupt (default 0) |
| FIFOE | FIFO read enable (disable while setting up) (default 1) |
| CP_FIFO_START (0xCC000020) | |
| 310 | |
| Access | R/W |
WARNING: This CP register is actually two 16 bit registers. Though it is big endian, a bug in the hardware means the two 16 bit halves will be swapped if you write to it 32-bit. You have been warned!
| CP_FIFO_END (0xCC000024) | |
| 310 | |
| Access | R/W |
WARNING: This CP register is actually two 16 bit registers. Though it is big endian, a bug in the hardware means the two 16 bit halves will be swapped if you write to it 32-bit. You have been warned!
| CP_FIFO_WP (0xCC000034) | |
| 310 | |
| Access | R/W |
WARNING: This CP register is actually two 16 bit registers. Though it is big endian, a bug in the hardware means the two 16 bit halves will be swapped if you write to it 32-bit. You have been warned!