Hardware/GX

Pixel Engine
Access
Broadway	Full
Starlet	None
Registers
Base	0x0c001000
Length	0x100
Access size	32 bits
Byte order	Big Endian
IRQs
Broadway	9,10

Command Processor
Access
Broadway	Full
Starlet	None
Registers
Base	0x0c000000
Length	0x80
Access size	16 bits
Byte order	Big Endian
IRQs
Broadway	11

GX FIFO

Graphics processor commands can be 8bit or 32bit, but they must be sent padded to 32bit. The CPU has a 32-bit FIFO accessed through the WGPIPE register at 0xcc008000 that will automatically pack data for you. All sorts of graphics data (vertices, primitives, etc) are sent through the FIFO.

The FIFO is a ring buffer in main memory. It is similar that it can be placed anywhere in main memory. One needs to initialize CP registers to describe the FIFO. Afterwards, all communications to the CP (including those forwarded to other units) are performed through the FIFO.

FIFO Setup

GX_CP_FIFO_STATUS (0xCC000000)
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	U											R	R	R	R	R
Field												BPInt	CmdIdle	RdIdle	UF	OF

Field	Description
BPInt	Indicates status of Blitting Processor interrupt?
CmdIdle	1: CP is not doing anything
RdIdle	1: CP is not reading anything (??)
UF	FIFO underflow (Determined by watermark registers?
OF	FIFO overflow ("")

GX_CP_CONTROL (0xCC000002)
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	U										R/W	R/W	R/W	R/W	R/W	R/W
Field											BPE	GPLE	UFInt	OFInt	CPInt	FIFOE

Field	Description
BPE	breakpoint enable (default 0)
GPLE	FIFO link enable (YAGCD says CP->PE?) (default 1)
UFInt	FIFO underflow interrupt (default 0)
OFInt	FIFO overflow interrupt (default 1)
CPInt	Command Processor interrupt (default 0)
FIFOE	FIFO read enable (disable while setting up) (default 1)

GX_CP_FIFO_START (0xCC000020)
	310
Access	R/W

WARNING: This CP register is actually two 16 bit registers. Though it is big endian, a bug in the hardware means the two 16 bit halves will be swapped if you write to it 32-bit. You have been warned!

GX_CP_FIFO_END (0xCC000024)
	310
Access	R/W

WARNING: This CP register is actually two 16 bit registers. Though it is big endian, a bug in the hardware means the two 16 bit halves will be swapped if you write to it 32-bit. You have been warned!

GX_CP_FIFO_WP (0xCC000034)
	310
Access	R/W

WARNING: This CP register is actually two 16 bit registers. Though it is big endian, a bug in the hardware means the two 16 bit halves will be swapped if you write to it 32-bit. You have been warned!

GX_PI_FIFO_WP (0xCC003014)
	310
Access	R/W

BP (blitting processor) registers

The BP registers are accessed by writing a 8-bit value of 0x61 to the FIFO, followed by 32 bit value. This value is a bit weird - the high 8 bits are the register, and the low 24 bits are the register value. More information on the BP can be found here.

CP (command processor) registers

The (internal, there are other CP registers mapped to main memory) CP registers are accessed by writing a 8-bit 0x08 to the FIFO, followed by 8 bits of something and then 32 bits of something. More information on the CP can be found here.

XF (transform unit) registers

The XF registers are accessed by first writing an 8-bit number of 0x10 to the FIFO, then a 32 bit value whose lower 16 bits are the address, and the upper 16 bits are the number of addresses to write to - 1. Following is one or more 32 bit datas. More info on the XF can be found here.