Difference between revisions of "Hardware/Memory Interface"
< Hardware
Jump to navigation
Jump to search
m (Bad size on MI_UNKNOWN2) |
m (IRQ, not INT) |
||
| Line 51: | Line 51: | ||
}} | }} | ||
| − | {{reg16 | | + | {{reg16 | MI_IRQMASK | addr = 0x0C00401C | fields = 6 | |
|11 |1 |1 |1 |1 |1 | | |11 |1 |1 |1 |1 |1 | | ||
|U |?/W |?/W |?/W |?/W |?/W | | |U |?/W |?/W |?/W |?/W |?/W | | ||
| Line 60: | Line 60: | ||
|ChAll|When set, all MI interrupts are enabled. | |ChAll|When set, all MI interrupts are enabled. | ||
}} | }} | ||
| − | {{reg16 | | + | {{reg16 | MI_IRQFLAG | addr = 0x0C00401E | fields = 6 | |
|11 |1 |1 |1 |1 |1 | | |11 |1 |1 |1 |1 |1 | | ||
|U |R/W |R/W |R/W |R/W |R/W | | |U |R/W |R/W |R/W |R/W |R/W | | ||
Revision as of 06:29, 6 July 2010
| Memory Interface | |
| Access | |
|---|---|
| Broadway | Full |
| Starlet | None |
| Registers | |
| Base | 0x0c004000 |
| Length | 0x80 |
| Access size | 16/32 bits |
| Byte order | Big Endian |
| IRQs | |
| Broadway | 7 |
| This Hardware-related article is a stub. You can help WiiBrew by expanding it. |
Protected memory is always 1 page long (page size is 1024 bytes), and you can specify only 4 protected regions. If the CPU tries to access the protected region in a way that is not allowed, an external interrupt will be raised. Because there are only 4 protected regions, there are a total of 4 possible interrupts which are called MEM_0, MEM_1, MEM_2 and MEM_3.
Registers
| MI_PROT_RGN0 (0x0C004000) | ||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | R/W | |||||||||||||||
| Field | Low 16 bits of protected address | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | R/W | |||||||||||||||
| Field | High 16 bits of protected address | |||||||||||||||
| MI_PROT_RGN1 (0x0C004004) | ||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | R/W | |||||||||||||||
| Field | Low 16 bits of protected address | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | R/W | |||||||||||||||
| Field | High 16 bits of protected address | |||||||||||||||
| MI_PROT_RGN2 (0x0C004008) | ||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | R/W | |||||||||||||||
| Field | Low 16 bits of protected address | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | R/W | |||||||||||||||
| Field | High 16 bits of protected address | |||||||||||||||
| MI_PROT_RGN3 (0x0C00400C) | ||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | R/W | |||||||||||||||
| Field | Low 16 bits of protected address | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | R/W | |||||||||||||||
| Field | High 16 bits of protected address | |||||||||||||||
| MI_PROT_TYPE (0x0C004010) | ||||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | U | R/W | R/W | R/W | R/W | |||||||||||
| Field | Ch3 | Ch2 | Ch1 | Ch0 | ||||||||||||
| Field | Description |
| ChX | 00: Access Denied, 01: Read Only, 10: Write Only, 11: Read/Write |
| MI_IRQMASK (0x0C00401C) | ||||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | U | ?/W | ?/W | ?/W | ?/W | ?/W | ||||||||||
| Field | ChAll | Ch3 | Ch2 | Ch1 | Ch0 | |||||||||||
| Field | Description |
| ChX | When set, interrupt from that channel is enabled. |
| ChAll | When set, all MI interrupts are enabled. |
| MI_IRQFLAG (0x0C00401E) | ||||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | U | R/W | R/W | R/W | R/W | R/W | ||||||||||
| Field | ChAll | Ch3 | Ch2 | Ch1 | Ch0 | |||||||||||
| Field | Description |
| ChX | When set, IRQ has been requested. Writing 1 clears it. |
| ChAll | All MI interrupts. (?) |
| MI_UNKNOWN1 (0x0C004020) | ||||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | U | ? | U | |||||||||||||
| Field | Unk | |||||||||||||||
| Field | Description |
| Unk | ? Set when MI interrupt has been asserted ? Should be cleared by interrupt handler |
| MI_PROT_ADDRLO (0x0C004022) | ||||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | R/? | U | ||||||||||||||
| Field | Low | |||||||||||||||
| MI_PROT_ADDRHI (0x0C004024) | ||||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | U | R/? | ||||||||||||||
| Field | High | |||||||||||||||
| Field | Description |
| High | Bits 29->16 of the address that the protection exception occurred on. |
| Low | Bits 15->5 of the address that the protection exception occurred on. |
| MI_TIMER0 (0x0C004032) | |
| 310 | |
| Access | R/? |
| MI_TIMER1 (0x0C004036) | |
| 310 | |
| Access | R/? |
| MI_TIMER2 (0x0C00403A) | |
| 310 | |
| Access | R/? |
| MI_TIMER3 (0x0C00403E) | |
| 310 | |
| Access | R/? |
| MI_TIMER4 (0x0C004042) | |
| 310 | |
| Access | R/? |
| MI_TIMER5 (0x0C004046) | |
| 310 | |
| Access | R/? |
| MI_TIMER6 (0x0C00404A) | |
| 310 | |
| Access | R/? |
| MI_TIMER7 (0x0C00404E) | |
| 310 | |
| Access | R/? |
| MI_TIMER8 (0x0C004052) | |
| 310 | |
| Access | R/? |
| MI_TIMER9 (0x0C004056) | |
| 310 | |
| Access | R/? |
| Field | Description |
| Timer | Writing anything to a timer resets it to 0. |
| MI_UNKNOWN2 (0x0C00405A) | ||||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | U | R/? | ||||||||||||||
| Field | ? | Unk | ||||||||||||||
| Field | Description |
| Unk | Possibly something timer related? |