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Difference between revisions of "Hardware/Memory Interface"

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(Added some basic info from YAGCD)
m (Added the rest of the pretty much known stuff. Timers still :/)
Line 50: Line 50:
 
{{regdesc
 
{{regdesc
 
|ChX|00: Access Denied, 01: Read Only, 10: Write Only, 11: Read/Write
 
|ChX|00: Access Denied, 01: Read Only, 10: Write Only, 11: Read/Write
 +
}}
 +
 +
{{reg16 | MI_INTMASK | addr = 0x0C00401C | fields = 6 |
 +
|11 |1    |1  |1  |1  |1  |
 +
|U  |?/W  |?/W |?/W |?/W |?/W |
 +
|  |ChAll |Ch3 |Ch2 |Ch1 |Ch0 |
 +
|}}
 +
{{regdesc
 +
|ChX|When set, interrupt from that channel is enabled.
 +
|ChAll|When set, all MI interrupts are enabled.
 +
}}
 +
{{reg16 | MI_INTFLAG | addr = 0x0C00401E | fields = 6 |
 +
|11 |1    |1  |1  |1  |1  |
 +
|U  |R/W  |R/W |R/W |R/W |R/W |
 +
|  |ChAll |Ch3 |Ch2 |Ch1 |Ch0 |
 +
|}}
 +
{{regdesc
 +
|ChX|When set, IRQ has been requested. Writing 1 clears it.
 +
|ChAll|All MI interrupts. (?)
 +
}}
 +
{{reg16 | MI_UNKNOWN1 | addr = 0x0C004020 | fields = 3 |
 +
|14 |1  |1 |
 +
|U  |?  |U |
 +
|  |Unk |  |
 +
|}}
 +
{{regdesc
 +
|Unk|? Set when MI interrupt has been asserted ? Should be cleared by interrupt handler
 +
}}
 +
 +
{{reg16 | MI_PROT_ADDRLO | addr = 0x0C004022 | fields = 2 |
 +
|11  |5 |
 +
|R/? |U |
 +
|Low |  |
 +
|}}
 +
{{reg16 | MI_PROT_ADDRHI | addr = 0x0C004024 | fields = 2 |
 +
|2 |14  |
 +
|U |R/?  |
 +
|  |High |
 +
|}}
 +
{{regdesc
 +
|High|Bits 29->16 of the address that the protection exception occurred on.
 +
|Low|Bits 15->5 of the address that the protection exception occurred on.
 
}}
 
}}

Revision as of 05:39, 6 July 2010

Memory Interface
Access
BroadwayFull
StarletNone
Registers
Base0x0c004000
Length0x80
Access size16/32 bits
Byte orderBig Endian
IRQs
Broadway7
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Protected memory is always 1 page long (page size is 1024 bytes), and you can specify only 4 protected regions. If the CPU tries to access the protected region in a way that is not allowed, an external interrupt will be raised. Because there are only 4 protected regions, there are a total of 4 possible interrupts which are called MEM_0, MEM_1, MEM_2 and MEM_3.

Registers

MI_PROT_RGN0 (0x0C004000)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access R/W
Field Low 16 bits of protected address
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W
Field High 16 bits of protected address

MI_PROT_RGN1 (0x0C004004)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access R/W
Field Low 16 bits of protected address
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W
Field High 16 bits of protected address

MI_PROT_RGN2 (0x0C004008)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access R/W
Field Low 16 bits of protected address
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W
Field High 16 bits of protected address

MI_PROT_RGN3 (0x0C00400C)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access R/W
Field Low 16 bits of protected address
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W
Field High 16 bits of protected address


MI_PROT_TYPE (0x0C004010)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access U R/W R/W R/W R/W
Field Ch3 Ch2 Ch1 Ch0
Field Description
ChX 00: Access Denied, 01: Read Only, 10: Write Only, 11: Read/Write


MI_INTMASK (0x0C00401C)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access U ?/W ?/W ?/W ?/W ?/W
Field ChAll Ch3 Ch2 Ch1 Ch0
Field Description
ChX When set, interrupt from that channel is enabled.
ChAll When set, all MI interrupts are enabled.

MI_INTFLAG (0x0C00401E)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access U R/W R/W R/W R/W R/W
Field ChAll Ch3 Ch2 Ch1 Ch0
Field Description
ChX When set, IRQ has been requested. Writing 1 clears it.
ChAll All MI interrupts. (?)

MI_UNKNOWN1 (0x0C004020)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access U ? U
Field Unk
Field Description
Unk ? Set when MI interrupt has been asserted ? Should be cleared by interrupt handler


MI_PROT_ADDRLO (0x0C004022)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/? U
Field Low

MI_PROT_ADDRHI (0x0C004024)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access U R/?
Field High
Field Description
High Bits 29->16 of the address that the protection exception occurred on.
Low Bits 15->5 of the address that the protection exception occurred on.
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